2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm-offsets.h>
32 *************************************************************************
34 * Jump vector table as in table 3.1 in [1]
36 *************************************************************************
42 ldr pc, _undefined_instruction
43 ldr pc, _software_interrupt
44 ldr pc, _prefetch_abort
50 _undefined_instruction: .word undefined_instruction
51 _software_interrupt: .word software_interrupt
52 _prefetch_abort: .word prefetch_abort
53 _data_abort: .word data_abort
54 _not_used: .word not_used
58 .balignl 16,0xdeadbeef
62 *************************************************************************
64 * Startup Code (called from the ARM reset exception vector)
66 * do important init only if we don't start from memory!
67 * relocate armboot to ram
69 * jump to second stage
71 *************************************************************************
76 .word CONFIG_SYS_TEXT_BASE
79 * These are defined in the board-specific linker script.
80 * Subtracting _start from them lets the linker put their
81 * relative position in the executable instead of leaving
86 .word __bss_start - _start
90 .word __bss_end__ - _start
97 /* IRQ stack memory (calculated at run-time) */
98 .globl IRQ_STACK_START
102 /* IRQ stack memory (calculated at run-time) */
103 .globl FIQ_STACK_START
108 /* IRQ stack memory (calculated at run-time) + 8 bytes */
109 .globl IRQ_STACK_START_IN
114 * the actual start code
119 * set the cpu to SVC32 mode
126 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
128 * relocate exception table
140 #ifdef CONFIG_S3C24X0
141 /* turn off the watchdog */
143 # if defined(CONFIG_S3C2400)
144 # define pWTCON 0x15300000
145 # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
146 # define CLKDIVN 0x14800014 /* clock divisor register */
148 # define pWTCON 0x53000000
149 # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
150 # define INTSUBMSK 0x4A00001C
151 # define CLKDIVN 0x4C000014 /* clock divisor register */
159 * mask all IRQs by setting all bits in the INTMR - default
164 # if defined(CONFIG_S3C2410)
170 /* FCLK:HCLK:PCLK = 1:2:4 */
171 /* default FCLK is 120 MHz ! */
175 #endif /* CONFIG_S3C24X0 */
178 * we do sys-critical inits only at reboot,
179 * not when booting from ram!
181 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
185 /* Set stackpointer in internal RAM to call board_init_f */
187 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
188 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
192 /*------------------------------------------------------------------------------*/
195 * void relocate_code (addr_sp, gd, addr_moni)
197 * This "function" does not return, instead it continues in RAM
198 * after relocating the monitor code.
203 mov r4, r0 /* save addr_sp */
204 mov r5, r1 /* save addr of gd */
205 mov r6, r2 /* save addr of destination */
207 /* Set up the stack */
213 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
214 beq clear_bss /* skip relocation */
215 mov r1, r6 /* r1 <- scratch for copy_loop */
216 ldr r3, _bss_start_ofs
217 add r2, r0, r3 /* r2 <- source end address */
220 ldmia r0!, {r9-r10} /* copy from source address [r0] */
221 stmia r1!, {r9-r10} /* copy to target address [r1] */
222 cmp r0, r2 /* until source end address [r2] */
225 #ifndef CONFIG_SPL_BUILD
227 * fix .rel.dyn relocations
229 ldr r0, _TEXT_BASE /* r0 <- Text base */
230 sub r9, r6, r0 /* r9 <- relocation offset */
231 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
232 add r10, r10, r0 /* r10 <- sym table in FLASH */
233 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
234 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
235 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
236 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
238 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
239 add r0, r0, r9 /* r0 <- location to fix up in RAM */
242 cmp r7, #23 /* relative fixup? */
244 cmp r7, #2 /* absolute fixup? */
246 /* ignore unknown type of fixup */
249 /* absolute fix: set location to (offset) symbol value */
250 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
251 add r1, r10, r1 /* r1 <- address of symbol in table */
252 ldr r1, [r1, #4] /* r1 <- symbol value */
253 add r1, r1, r9 /* r1 <- relocated sym addr */
256 /* relative fix: increase location by offset */
261 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
267 #ifndef CONFIG_SPL_BUILD
268 ldr r0, _bss_start_ofs
270 mov r4, r6 /* reloc addr */
273 mov r2, #0x00000000 /* clear */
275 clbss_l:cmp r0, r1 /* clear loop... */
276 bhs clbss_e /* if reached end of bss, exit */
287 * We are done. Do not return, instead branch to second part of board
288 * initialization, now running from RAM.
290 #ifdef CONFIG_NAND_SPL
291 ldr r0, _nand_boot_ofs
297 ldr r0, _board_init_r_ofs
301 /* setup parameters for board_init_r */
302 mov r0, r5 /* gd_t */
303 mov r1, r6 /* dest_addr */
308 .word board_init_r - _start
312 .word __rel_dyn_start - _start
314 .word __rel_dyn_end - _start
316 .word __dynsym_start - _start
319 *************************************************************************
321 * CPU_init_critical registers
323 * setup important registers
324 * setup memory timing
326 *************************************************************************
330 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
333 * flush v4 I/D caches
336 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
337 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
340 * disable MMU stuff and caches
342 mrc p15, 0, r0, c1, c0, 0
343 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
344 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
345 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
346 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
347 mcr p15, 0, r0, c1, c0, 0
350 * before relocating, we have to setup RAM timing
351 * because memory timing is board-dependend, you will
352 * find a lowlevel_init.S in your board directory.
360 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
363 *************************************************************************
367 *************************************************************************
373 #define S_FRAME_SIZE 72
395 #define MODE_SVC 0x13
399 * use bad_save_user_regs for abort/prefetch/undef/swi ...
400 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
403 .macro bad_save_user_regs
404 sub sp, sp, #S_FRAME_SIZE
405 stmia sp, {r0 - r12} @ Calling r0-r12
406 ldr r2, IRQ_STACK_START_IN
407 ldmia r2, {r2 - r3} @ get pc, cpsr
408 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
412 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
416 .macro irq_save_user_regs
417 sub sp, sp, #S_FRAME_SIZE
418 stmia sp, {r0 - r12} @ Calling r0-r12
420 stmdb r7, {sp, lr}^ @ Calling SP, LR
421 str lr, [r7, #0] @ Save calling PC
423 str r6, [r7, #4] @ Save CPSR
424 str r0, [r7, #8] @ Save OLD_R0
428 .macro irq_restore_user_regs
429 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
431 ldr lr, [sp, #S_PC] @ Get PC
432 add sp, sp, #S_FRAME_SIZE
433 /* return & move spsr_svc into cpsr */
438 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
440 str lr, [r13] @ save caller lr / spsr
444 mov r13, #MODE_SVC @ prepare SVC-Mode
451 .macro get_irq_stack @ setup IRQ stack
452 ldr sp, IRQ_STACK_START
455 .macro get_fiq_stack @ setup FIQ stack
456 ldr sp, FIQ_STACK_START
463 undefined_instruction:
466 bl do_undefined_instruction
472 bl do_software_interrupt
492 #ifdef CONFIG_USE_IRQ
499 irq_restore_user_regs
504 /* someone ought to write a more effiction fiq_save_user_regs */
507 irq_restore_user_regs