2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm-offsets.h>
16 *************************************************************************
18 * Startup Code (called from the ARM reset exception vector)
20 * do important init only if we don't start from memory!
21 * relocate armboot to ram
23 * jump to second stage
25 *************************************************************************
32 * set the cpu to SVC32 mode
39 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
41 * relocate exception table
54 /* turn off the watchdog */
56 # if defined(CONFIG_S3C2400)
57 # define pWTCON 0x15300000
58 # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
59 # define CLKDIVN 0x14800014 /* clock divisor register */
61 # define pWTCON 0x53000000
62 # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
63 # define INTSUBMSK 0x4A00001C
64 # define CLKDIVN 0x4C000014 /* clock divisor register */
72 * mask all IRQs by setting all bits in the INTMR - default
77 # if defined(CONFIG_S3C2410)
83 /* FCLK:HCLK:PCLK = 1:2:4 */
84 /* default FCLK is 120 MHz ! */
88 #endif /* CONFIG_S3C24X0 */
91 * we do sys-critical inits only at reboot,
92 * not when booting from ram!
94 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
100 /*------------------------------------------------------------------------------*/
102 .globl c_runtime_cpu_setup
108 *************************************************************************
110 * CPU_init_critical registers
112 * setup important registers
113 * setup memory timing
115 *************************************************************************
119 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
122 * flush v4 I/D caches
125 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
126 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
129 * disable MMU stuff and caches
131 mrc p15, 0, r0, c1, c0, 0
132 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
133 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
134 orr r0, r0, #0x00000002 @ set bit 1 (A) Align
135 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
136 mcr p15, 0, r0, c1, c0, 0
139 * before relocating, we have to setup RAM timing
140 * because memory timing is board-dependend, you will
141 * find a lowlevel_init.S in your board directory.
149 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */