2 * armboot - Startup Code for ARM920 CPU-core
4 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
5 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
6 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm-offsets.h>
16 *************************************************************************
18 * Jump vector table as in table 3.1 in [1]
20 *************************************************************************
26 ldr pc, _undefined_instruction
27 ldr pc, _software_interrupt
28 ldr pc, _prefetch_abort
34 _undefined_instruction: .word undefined_instruction
35 _software_interrupt: .word software_interrupt
36 _prefetch_abort: .word prefetch_abort
37 _data_abort: .word data_abort
38 _not_used: .word not_used
42 .balignl 16,0xdeadbeef
46 *************************************************************************
48 * Startup Code (called from the ARM reset exception vector)
50 * do important init only if we don't start from memory!
51 * relocate armboot to ram
53 * jump to second stage
55 *************************************************************************
60 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
61 .word CONFIG_SPL_TEXT_BASE
63 .word CONFIG_SYS_TEXT_BASE
67 * These are defined in the board-specific linker script.
68 * Subtracting _start from them lets the linker put their
69 * relative position in the executable instead of leaving
74 .word __bss_start - _start
78 .word __bss_end - _start
85 /* IRQ stack memory (calculated at run-time) */
86 .globl IRQ_STACK_START
90 /* IRQ stack memory (calculated at run-time) */
91 .globl FIQ_STACK_START
96 /* IRQ stack memory (calculated at run-time) + 8 bytes */
97 .globl IRQ_STACK_START_IN
102 * the actual start code
107 * set the cpu to SVC32 mode
114 #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
116 * relocate exception table
128 #ifdef CONFIG_S3C24X0
129 /* turn off the watchdog */
131 # if defined(CONFIG_S3C2400)
132 # define pWTCON 0x15300000
133 # define INTMSK 0x14400008 /* Interrupt-Controller base addresses */
134 # define CLKDIVN 0x14800014 /* clock divisor register */
136 # define pWTCON 0x53000000
137 # define INTMSK 0x4A000008 /* Interrupt-Controller base addresses */
138 # define INTSUBMSK 0x4A00001C
139 # define CLKDIVN 0x4C000014 /* clock divisor register */
147 * mask all IRQs by setting all bits in the INTMR - default
152 # if defined(CONFIG_S3C2410)
158 /* FCLK:HCLK:PCLK = 1:2:4 */
159 /* default FCLK is 120 MHz ! */
163 #endif /* CONFIG_S3C24X0 */
166 * we do sys-critical inits only at reboot,
167 * not when booting from ram!
169 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
175 /*------------------------------------------------------------------------------*/
177 .globl c_runtime_cpu_setup
183 *************************************************************************
185 * CPU_init_critical registers
187 * setup important registers
188 * setup memory timing
190 *************************************************************************
194 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
197 * flush v4 I/D caches
200 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
201 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
204 * disable MMU stuff and caches
206 mrc p15, 0, r0, c1, c0, 0
207 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
208 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
209 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
210 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
211 mcr p15, 0, r0, c1, c0, 0
214 * before relocating, we have to setup RAM timing
215 * because memory timing is board-dependend, you will
216 * find a lowlevel_init.S in your board directory.
224 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
227 *************************************************************************
231 *************************************************************************
237 #define S_FRAME_SIZE 72
259 #define MODE_SVC 0x13
263 * use bad_save_user_regs for abort/prefetch/undef/swi ...
264 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
267 .macro bad_save_user_regs
268 sub sp, sp, #S_FRAME_SIZE
269 stmia sp, {r0 - r12} @ Calling r0-r12
270 ldr r2, IRQ_STACK_START_IN
271 ldmia r2, {r2 - r3} @ get pc, cpsr
272 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
276 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
280 .macro irq_save_user_regs
281 sub sp, sp, #S_FRAME_SIZE
282 stmia sp, {r0 - r12} @ Calling r0-r12
284 stmdb r7, {sp, lr}^ @ Calling SP, LR
285 str lr, [r7, #0] @ Save calling PC
287 str r6, [r7, #4] @ Save CPSR
288 str r0, [r7, #8] @ Save OLD_R0
292 .macro irq_restore_user_regs
293 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
295 ldr lr, [sp, #S_PC] @ Get PC
296 add sp, sp, #S_FRAME_SIZE
297 /* return & move spsr_svc into cpsr */
302 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
304 str lr, [r13] @ save caller lr / spsr
308 mov r13, #MODE_SVC @ prepare SVC-Mode
315 .macro get_irq_stack @ setup IRQ stack
316 ldr sp, IRQ_STACK_START
319 .macro get_fiq_stack @ setup FIQ stack
320 ldr sp, FIQ_STACK_START
327 undefined_instruction:
330 bl do_undefined_instruction
336 bl do_software_interrupt
356 #ifdef CONFIG_USE_IRQ
363 irq_restore_user_regs
368 /* someone ought to write a more effiction fiq_save_user_regs */
371 irq_restore_user_regs