3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * Contributor: Mahavir Jain <mjain@marvell.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 #include <asm/arch/armada100.h>
31 * Refer Section A.6 in Datasheet
33 struct armd1tmr_registers {
34 u32 clk_ctrl; /* Timer clk control reg */
35 u32 match[9]; /* Timer match registers */
36 u32 count[3]; /* Timer count registers */
39 u32 preload[3]; /* Timer preload value */
47 u32 cer; /* Timer count enable reg */
56 #define TIMER 0 /* Use TIMER 0 */
57 /* Each timer has 3 match registers */
58 #define MATCH_CMP(x) ((3 * TIMER) + x)
59 #define TIMER_LOAD_VAL 0xffffffff
60 #define COUNT_RD_REQ 0x1
62 DECLARE_GLOBAL_DATA_PTR;
63 /* Using gd->tbu from timestamp and gd->tbl for lastdec */
65 /* For preventing risk of instability in reading counter value,
66 * first set read request to register cvwr and then read same
67 * register after it captures counter value.
69 ulong read_timer(void)
71 struct armd1tmr_registers *armd1timers =
72 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
73 volatile int loop=100;
75 writel(COUNT_RD_REQ, &armd1timers->cvwr);
77 return(readl(&armd1timers->cvwr));
80 void reset_timer_masked(void)
83 gd->tbl = read_timer();
87 ulong get_timer_masked(void)
89 ulong now = read_timer();
93 gd->tbu += now - gd->tbl;
95 /* we have an overflow ... */
96 gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
103 void reset_timer(void)
105 reset_timer_masked();
108 ulong get_timer(ulong base)
110 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
114 void set_timer(ulong t)
119 void __udelay(unsigned long usec)
124 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
125 endtime = get_timer_masked() + delayticks;
127 while (get_timer_masked() < endtime);
135 struct armd1apb1_registers *apb1clkres =
136 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
137 struct armd1tmr_registers *armd1timers =
138 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
140 /* Enable Timer clock at 3.25 MHZ */
141 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
143 /* load value into timer */
144 writel(0x0, &armd1timers->clk_ctrl);
145 /* Use Timer 0 Match Resiger 0 */
146 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
147 /* Preload value is 0 */
148 writel(0x0, &armd1timers->preload[TIMER]);
149 /* Enable match comparator 0 for Timer 0 */
150 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
153 writel(0x1, &armd1timers->cer);
154 /* init the gd->tbu and gd->tbl value */
155 reset_timer_masked();
160 #define MPMU_APRR_WDTR (1<<4)
161 #define TMR_WFAR 0xbaba /* WDT Register First key */
162 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
165 * This function uses internal Watchdog Timer
166 * based reset mechanism.
167 * Steps to write watchdog registers (protected access)
168 * 1. Write key value to TMR_WFAR reg.
169 * 2. Write key value to TMP_WSAR reg.
170 * 3. Perform write operation.
172 void reset_cpu (unsigned long ignored)
174 struct armd1mpmu_registers *mpmu =
175 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
176 struct armd1tmr_registers *armd1timers =
177 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
180 /* negate hardware reset to the WDT after system reset */
181 val = readl(&mpmu->aprr);
182 val = val | MPMU_APRR_WDTR;
183 writel(val, &mpmu->aprr);
185 /* reset/enable WDT clock */
186 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
187 readl(&mpmu->wdtpcr);
188 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
189 readl(&mpmu->wdtpcr);
191 /* clear previous WDT status */
192 writel(TMR_WFAR, &armd1timers->wfar);
193 writel(TMP_WSAR, &armd1timers->wsar);
194 writel(0, &armd1timers->wdt_sts);
196 /* set match counter */
197 writel(TMR_WFAR, &armd1timers->wfar);
198 writel(TMP_WSAR, &armd1timers->wsar);
199 writel(0xf, &armd1timers->wdt_match_r);
201 /* enable WDT reset */
202 writel(TMR_WFAR, &armd1timers->wfar);
203 writel(TMP_WSAR, &armd1timers->wsar);
204 writel(0x3, &armd1timers->wdt_match_en);