3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * Contributor: Mahavir Jain <mjain@marvell.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/armada100.h>
16 * Refer Section A.6 in Datasheet
18 struct armd1tmr_registers {
19 u32 clk_ctrl; /* Timer clk control reg */
20 u32 match[9]; /* Timer match registers */
21 u32 count[3]; /* Timer count registers */
24 u32 preload[3]; /* Timer preload value */
32 u32 cer; /* Timer count enable reg */
41 #define TIMER 0 /* Use TIMER 0 */
42 /* Each timer has 3 match registers */
43 #define MATCH_CMP(x) ((3 * TIMER) + x)
44 #define TIMER_LOAD_VAL 0xffffffff
45 #define COUNT_RD_REQ 0x1
47 DECLARE_GLOBAL_DATA_PTR;
48 /* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
50 /* For preventing risk of instability in reading counter value,
51 * first set read request to register cvwr and then read same
52 * register after it captures counter value.
54 ulong read_timer(void)
56 struct armd1tmr_registers *armd1timers =
57 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
58 volatile int loop=100;
60 writel(COUNT_RD_REQ, &armd1timers->cvwr);
62 return(readl(&armd1timers->cvwr));
65 ulong get_timer_masked(void)
67 ulong now = read_timer();
69 if (now >= gd->arch.tbl) {
71 gd->arch.tbu += now - gd->arch.tbl;
73 /* we have an overflow ... */
74 gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
81 ulong get_timer(ulong base)
83 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
87 void __udelay(unsigned long usec)
92 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
93 endtime = get_timer_masked() + delayticks;
95 while (get_timer_masked() < endtime);
103 struct armd1apb1_registers *apb1clkres =
104 (struct armd1apb1_registers *) ARMD1_APBC1_BASE;
105 struct armd1tmr_registers *armd1timers =
106 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
108 /* Enable Timer clock at 3.25 MHZ */
109 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
111 /* load value into timer */
112 writel(0x0, &armd1timers->clk_ctrl);
113 /* Use Timer 0 Match Resiger 0 */
114 writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
115 /* Preload value is 0 */
116 writel(0x0, &armd1timers->preload[TIMER]);
117 /* Enable match comparator 0 for Timer 0 */
118 writel(0x1, &armd1timers->preload_ctrl[TIMER]);
121 writel(0x1, &armd1timers->cer);
122 /* init the gd->arch.tbu and gd->arch.tbl value */
123 gd->arch.tbl = read_timer();
129 #define MPMU_APRR_WDTR (1<<4)
130 #define TMR_WFAR 0xbaba /* WDT Register First key */
131 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
134 * This function uses internal Watchdog Timer
135 * based reset mechanism.
136 * Steps to write watchdog registers (protected access)
137 * 1. Write key value to TMR_WFAR reg.
138 * 2. Write key value to TMP_WSAR reg.
139 * 3. Perform write operation.
141 void reset_cpu (unsigned long ignored)
143 struct armd1mpmu_registers *mpmu =
144 (struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
145 struct armd1tmr_registers *armd1timers =
146 (struct armd1tmr_registers *) ARMD1_TIMER_BASE;
149 /* negate hardware reset to the WDT after system reset */
150 val = readl(&mpmu->aprr);
151 val = val | MPMU_APRR_WDTR;
152 writel(val, &mpmu->aprr);
154 /* reset/enable WDT clock */
155 writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
156 readl(&mpmu->wdtpcr);
157 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
158 readl(&mpmu->wdtpcr);
160 /* clear previous WDT status */
161 writel(TMR_WFAR, &armd1timers->wfar);
162 writel(TMP_WSAR, &armd1timers->wsar);
163 writel(0, &armd1timers->wdt_sts);
165 /* set match counter */
166 writel(TMR_WFAR, &armd1timers->wfar);
167 writel(TMP_WSAR, &armd1timers->wsar);
168 writel(0xf, &armd1timers->wdt_match_r);
170 /* enable WDT reset */
171 writel(TMR_WFAR, &armd1timers->wfar);
172 writel(TMP_WSAR, &armd1timers->wsar);
173 writel(0x3, &armd1timers->wdt_match_en);
179 * This function is derived from PowerPC code (read timebase as long long).
180 * On ARM it just returns the timer value.
182 unsigned long long get_ticks(void)
188 * This function is derived from PowerPC code (timebase clock frequency).
189 * On ARM it returns the number of timer ticks per second.
191 ulong get_tbclk (void)
193 return (ulong)CONFIG_SYS_HZ;