3 * Ilya Yanok, EmCraft Systems
5 * SPDX-License-Identifier: GPL-2.0+
7 #include <linux/types.h>
10 #ifndef CONFIG_SYS_DCACHE_OFF
12 #ifndef CONFIG_SYS_CACHELINE_SIZE
13 #define CONFIG_SYS_CACHELINE_SIZE 32
16 void invalidate_dcache_all(void)
18 asm volatile("mcr p15, 0, %0, c7, c6, 0\n" : : "r"(0));
21 void flush_dcache_all(void)
25 "mrc p15, 0, r15, c7, c14, 3\n"
27 "mcr p15, 0, %0, c7, c10, 4\n"
32 static int check_cache_range(unsigned long start, unsigned long stop)
36 if (start & (CONFIG_SYS_CACHELINE_SIZE - 1))
39 if (stop & (CONFIG_SYS_CACHELINE_SIZE - 1))
43 debug("CACHE: Misaligned operation at range [%08lx, %08lx]\n",
49 void invalidate_dcache_range(unsigned long start, unsigned long stop)
51 if (!check_cache_range(start, stop))
54 while (start < stop) {
55 asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
56 start += CONFIG_SYS_CACHELINE_SIZE;
60 void flush_dcache_range(unsigned long start, unsigned long stop)
62 if (!check_cache_range(start, stop))
65 while (start < stop) {
66 asm volatile("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(start));
67 start += CONFIG_SYS_CACHELINE_SIZE;
70 asm volatile("mcr p15, 0, %0, c7, c10, 4\n" : : "r"(0));
72 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
73 void invalidate_dcache_all(void)
77 void flush_dcache_all(void)
80 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
83 * Stub implementations for l2 cache operations
85 __weak void l2_cache_disable(void) {}