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Merge branch 'master' of git://git.denx.de/u-boot-arm
[u-boot] / arch / arm / cpu / arm926ejs / davinci / dm365_lowlevel.c
1 /*
2  * SoC-specific lowlevel code for tms320dm365 and similar chips
3  * Actually used for booting from NAND with nand_spl.
4  *
5  * Copyright (C) 2011
6  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
7  *
8  * See file CREDITS for list of people who contributed to this
9  * project.
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  *
16  * This program is distributed in the hope that it will be useful,
17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19  * GNU General Public License for more details.
20  *
21  * You should have received a copy of the GNU General Public License
22  * along with this program; if not, write to the Free Software
23  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24  */
25 #include <common.h>
26 #include <nand.h>
27 #include <ns16550.h>
28 #include <post.h>
29 #include <asm/arch/dm365_lowlevel.h>
30 #include <asm/arch/hardware.h>
31
32 void dm365_waitloop(unsigned long loopcnt)
33 {
34         unsigned long   i;
35
36         for (i = 0; i < loopcnt; i++)
37                 asm("   NOP");
38 }
39
40 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv)
41 {
42         unsigned int clksrc = 0x0;
43
44         /* Power up the PLL */
45         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN);
46
47         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9);
48         setbits_le32(&dv_pll0_regs->pllctl,
49                 clksrc << PLLCTL_CLOCK_MODE_SHIFT);
50
51         /*
52          * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
53          * through MMR
54          */
55         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC);
56
57         /* Set PLLEN=0 => PLL BYPASS MODE */
58         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
59
60         dm365_waitloop(150);
61
62          /* PLLRST=1(reset assert) */
63         setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
64
65         dm365_waitloop(300);
66
67         /*Bring PLL out of Reset*/
68         clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST);
69
70         /* Program the Multiper and Pre-Divider for PLL1 */
71         writel(pllmult, &dv_pll0_regs->pllm);
72         writel(prediv, &dv_pll0_regs->prediv);
73
74         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
75         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
76                 PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
77         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
78         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
79                 &dv_pll0_regs->secctl);
80         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
81         writel(PLLSECCTL_STOPMODE, &dv_pll0_regs->secctl);
82         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
83         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll0_regs->secctl);
84
85         /* Program the PostDiv for PLL1 */
86         writel(PLL_POSTDEN, &dv_pll0_regs->postdiv);
87
88         /* Post divider setting for PLL1 */
89         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV1, &dv_pll0_regs->plldiv1);
90         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV2, &dv_pll0_regs->plldiv2);
91         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV3, &dv_pll0_regs->plldiv3);
92         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV4, &dv_pll0_regs->plldiv4);
93         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV5, &dv_pll0_regs->plldiv5);
94         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV6, &dv_pll0_regs->plldiv6);
95         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV7, &dv_pll0_regs->plldiv7);
96         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV8, &dv_pll0_regs->plldiv8);
97         writel(CONFIG_SYS_DM36x_PLL1_PLLDIV9, &dv_pll0_regs->plldiv9);
98
99         dm365_waitloop(300);
100
101         /* Set the GOSET bit */
102         writel(PLLCMD_GOSET, &dv_pll0_regs->pllcmd); /* Go */
103
104         dm365_waitloop(300);
105
106         /* Wait for PLL to LOCK */
107         while (!((readl(&dv_sys_module_regs->pll0_config) & PLL0_LOCK)
108                 == PLL0_LOCK))
109                 ;
110
111         /* Enable the PLL Bit of PLLCTL*/
112         setbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN);
113
114         return 0;
115 }
116
117 int dm365_pll2_init(unsigned long pllm, unsigned long prediv)
118 {
119         unsigned int clksrc = 0x0;
120
121         /* Power up the PLL*/
122         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN);
123
124         /*
125          * Select the Clock Mode as Onchip Oscilator or External Clock on
126          * MXI pin
127          * VDB has input on MXI pin
128          */
129         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9);
130         setbits_le32(&dv_pll1_regs->pllctl,
131                 clksrc << PLLCTL_CLOCK_MODE_SHIFT);
132
133         /*
134          * Set PLLENSRC '0', PLL Enable(PLLEN) selection is controlled
135          * through MMR
136          */
137         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC);
138
139         /* Set PLLEN=0 => PLL BYPASS MODE */
140         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
141
142         dm365_waitloop(50);
143
144          /* PLLRST=1(reset assert) */
145         setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
146
147         dm365_waitloop(300);
148
149         /* Bring PLL out of Reset */
150         clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST);
151
152         /* Program the Multiper and Pre-Divider for PLL2 */
153         writel(pllm, &dv_pll1_regs->pllm);
154         writel(prediv, &dv_pll1_regs->prediv);
155
156         writel(PLL_POSTDEN, &dv_pll1_regs->postdiv);
157
158         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1 */
159         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE |
160                 PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
161         /* Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0 */
162         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TENABLEDIV | PLLSECCTL_TENABLE,
163                 &dv_pll1_regs->secctl);
164         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0 */
165         writel(PLLSECCTL_STOPMODE, &dv_pll1_regs->secctl);
166         /* Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1 */
167         writel(PLLSECCTL_STOPMODE | PLLSECCTL_TINITZ, &dv_pll1_regs->secctl);
168
169         /* Post divider setting for PLL2 */
170         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV1, &dv_pll1_regs->plldiv1);
171         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV2, &dv_pll1_regs->plldiv2);
172         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV3, &dv_pll1_regs->plldiv3);
173         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV4, &dv_pll1_regs->plldiv4);
174         writel(CONFIG_SYS_DM36x_PLL2_PLLDIV5, &dv_pll1_regs->plldiv5);
175
176         /* GoCmd for PostDivider to take effect */
177         writel(PLLCMD_GOSET, &dv_pll1_regs->pllcmd);
178
179         dm365_waitloop(150);
180
181         /* Wait for PLL to LOCK */
182         while (!((readl(&dv_sys_module_regs->pll1_config) & PLL1_LOCK)
183                 == PLL1_LOCK))
184                 ;
185
186         dm365_waitloop(4100);
187
188         /* Enable the PLL2 */
189         setbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN);
190
191         /* do this after PLL's have been set up */
192         writel(CONFIG_SYS_DM36x_PERI_CLK_CTRL,
193                 &dv_sys_module_regs->peri_clkctl);
194
195         return 0;
196 }
197
198 int dm365_ddr_setup(void)
199 {
200         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
201         clrbits_le32(&dv_sys_module_regs->vtpiocr,
202                 VPTIO_IOPWRDN | VPTIO_CLRZ | VPTIO_LOCK | VPTIO_PWRDN);
203
204         /* Set bit CLRZ (bit 13) */
205         setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_CLRZ);
206
207         /* Check VTP READY Status */
208         while (!(readl(&dv_sys_module_regs->vtpiocr) & VPTIO_RDY))
209                 ;
210
211         /* Set bit VTP_IOPWRDWN bit 14 for DDR input buffers) */
212         setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_IOPWRDN);
213
214         /* Set bit LOCK(bit7) */
215         setbits_le32(&dv_sys_module_regs->vtpiocr, VPTIO_LOCK);
216
217         /*
218          * Powerdown VTP as it is locked (bit 6)
219          * Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
220          */
221         setbits_le32(&dv_sys_module_regs->vtpiocr,
222                 VPTIO_IOPWRDN | VPTIO_PWRDN);
223
224         /* Wait for calibration to complete */
225         dm365_waitloop(150);
226
227         /* Set the DDR2 to synreset, then enable it again */
228         lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
229         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
230
231         writel(CONFIG_SYS_DM36x_DDR2_DDRPHYCR, &dv_ddr2_regs_ctrl->ddrphycr);
232
233         /* Program SDRAM Bank Config Register */
234         writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_BOOTUNLOCK),
235                 &dv_ddr2_regs_ctrl->sdbcr);
236         writel((CONFIG_SYS_DM36x_DDR2_SDBCR | DV_DDR_TIMUNLOCK),
237                 &dv_ddr2_regs_ctrl->sdbcr);
238
239         /* Program SDRAM Timing Control Register1 */
240         writel(CONFIG_SYS_DM36x_DDR2_SDTIMR, &dv_ddr2_regs_ctrl->sdtimr);
241         /* Program SDRAM Timing Control Register2 */
242         writel(CONFIG_SYS_DM36x_DDR2_SDTIMR2, &dv_ddr2_regs_ctrl->sdtimr2);
243
244         writel(CONFIG_SYS_DM36x_DDR2_PBBPR, &dv_ddr2_regs_ctrl->pbbpr);
245
246         writel(CONFIG_SYS_DM36x_DDR2_SDBCR, &dv_ddr2_regs_ctrl->sdbcr);
247
248         /* Program SDRAM Refresh Control Register */
249         writel(CONFIG_SYS_DM36x_DDR2_SDRCR, &dv_ddr2_regs_ctrl->sdrcr);
250
251         lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
252         lpsc_on(DAVINCI_LPSC_DDR_EMIF);
253
254         return 0;
255 }
256
257 static void dm365_vpss_sync_reset(void)
258 {
259         unsigned int PdNum = 0;
260
261         /* VPSS_CLKMD 1:1 */
262         setbits_le32(&dv_sys_module_regs->vpss_clkctl,
263                 VPSS_CLK_CTL_VPSS_CLKMD);
264
265         /* LPSC SyncReset DDR Clock Enable */
266         writel(((readl(&dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]) &
267                 ~PSC_MD_STATE_MSK) | PSC_SYNCRESET),
268                 &dv_psc_regs->mdctl[DAVINCI_LPSC_VPSSMASTER]);
269
270         writel((1 << PdNum), &dv_psc_regs->ptcmd);
271
272         while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT) == 0))
273                 ;
274         while (!((readl(&dv_psc_regs->mdstat[DAVINCI_LPSC_VPSSMASTER]) &
275                 PSC_MD_STATE_MSK) == PSC_SYNCRESET))
276                 ;
277 }
278
279 static void dm365_por_reset(void)
280 {
281         struct davinci_timer *wdog =
282                 (struct davinci_timer *)DAVINCI_WDOG_BASE;
283
284         if (readl(&dv_pll0_regs->rstype) &
285                 (PLL_RSTYPE_POR | PLL_RSTYPE_XWRST)) {
286                 dm365_vpss_sync_reset();
287
288                 writel(DV_TMPBUF_VAL, TMPBUF);
289                 setbits_le32(TMPSTATUS, FLAG_PORRST);
290                 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
291                 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
292
293                 while (1);
294         }
295 }
296
297 static void dm365_wdt_reset(void)
298 {
299         struct davinci_timer *wdog =
300                 (struct davinci_timer *)DAVINCI_WDOG_BASE;
301
302         if (readl(TMPBUF) != DV_TMPBUF_VAL) {
303                 writel(DV_TMPBUF_VAL, TMPBUF);
304                 setbits_le32(TMPSTATUS, FLAG_PORRST);
305                 setbits_le32(TMPSTATUS, FLAG_FLGOFF);
306
307                 dm365_waitloop(100);
308
309                 dm365_vpss_sync_reset();
310
311                 writel(DV_WDT_ENABLE_SYS_RESET, &wdog->na1);
312                 writel(DV_WDT_TRIGGER_SYS_RESET, &wdog->na2);
313
314                 while (1);
315         }
316 }
317
318 static void dm365_wdt_flag_on(void)
319 {
320         /* VPSS_CLKMD 1:2 */
321         clrbits_le32(&dv_sys_module_regs->vpss_clkctl,
322                 VPSS_CLK_CTL_VPSS_CLKMD);
323         writel(0, TMPBUF);
324         setbits_le32(TMPSTATUS, FLAG_FLGON);
325 }
326
327 void dm365_psc_init(void)
328 {
329         unsigned char i = 0;
330         unsigned char lpsc_start;
331         unsigned char lpsc_end, lpscgroup, lpscmin, lpscmax;
332         unsigned int  PdNum = 0;
333
334         lpscmin = 0;
335         lpscmax = 2;
336
337         for (lpscgroup = lpscmin; lpscgroup <= lpscmax; lpscgroup++) {
338                 if (lpscgroup == 0) {
339                         /* Enabling LPSC 3 to 28 SCR first */
340                         lpsc_start = DAVINCI_LPSC_VPSSMSTR;
341                         lpsc_end   = DAVINCI_LPSC_TIMER1;
342                 } else if (lpscgroup == 1) { /* Skip locked LPSCs [29-37] */
343                         lpsc_start = DAVINCI_LPSC_CFG5;
344                         lpsc_end   = DAVINCI_LPSC_VPSSMASTER;
345                 } else {
346                         lpsc_start = DAVINCI_LPSC_MJCP;
347                         lpsc_end   = DAVINCI_LPSC_HDVICP;
348                 }
349
350                 /* NEXT=0x3, Enable LPSC's */
351                 for (i = lpsc_start; i <= lpsc_end; i++)
352                         setbits_le32(&dv_psc_regs->mdctl[i], PSC_ENABLE);
353
354                 /*
355                  * Program goctl to start transition sequence for LPSCs
356                  * CSL_PSC_0_REGS->PTCMD = (1<<PdNum); Kick off Power
357                  * Domain 0 Modules
358                  */
359                 writel((1 << PdNum), &dv_psc_regs->ptcmd);
360
361                 /*
362                  * Wait for GOSTAT = NO TRANSITION from PSC for Powerdomain 0
363                  */
364                 while (!(((readl(&dv_psc_regs->ptstat) >> PdNum) & PSC_GOSTAT)
365                         == 0))
366                         ;
367
368                 /* Wait for MODSTAT = ENABLE from LPSC's */
369                 for (i = lpsc_start; i <= lpsc_end; i++)
370                         while (!((readl(&dv_psc_regs->mdstat[i]) &
371                                 PSC_MD_STATE_MSK) == PSC_ENABLE))
372                                 ;
373         }
374 }
375
376 static void dm365_emif_init(void)
377 {
378         writel(CONFIG_SYS_DM36x_AWCCR, &davinci_emif_regs->awccr);
379         writel(CONFIG_SYS_DM36x_AB1CR, &davinci_emif_regs->ab1cr);
380
381         setbits_le32(&davinci_emif_regs->nandfcr, DAVINCI_NANDFCR_CS2NAND);
382
383         writel(CONFIG_SYS_DM36x_AB2CR, &davinci_emif_regs->ab2cr);
384
385         return;
386 }
387
388 void dm365_pinmux_ctl(unsigned long offset, unsigned long mask,
389         unsigned long value)
390 {
391         clrbits_le32(&dv_sys_module_regs->pinmux[offset], mask);
392         setbits_le32(&dv_sys_module_regs->pinmux[offset], (mask & value));
393 }
394
395 __attribute__((weak))
396 void board_gpio_init(void)
397 {
398         return;
399 }
400
401 #if defined(CONFIG_POST)
402 int post_log(char *format, ...)
403 {
404         return 0;
405 }
406 #endif
407
408 void dm36x_lowlevel_init(ulong bootflag)
409 {
410         struct davinci_uart_ctrl_regs *davinci_uart_ctrl_regs =
411                 (struct davinci_uart_ctrl_regs *)(CONFIG_SYS_NS16550_COM1 +
412                 DAVINCI_UART_CTRL_BASE);
413
414         /* Mask all interrupts */
415         writel(DV_AINTC_INTCTL_IDMODE, &dv_aintc_regs->intctl);
416         writel(0x0, &dv_aintc_regs->eabase);
417         writel(0x0, &dv_aintc_regs->eint0);
418         writel(0x0, &dv_aintc_regs->eint1);
419
420         /* Clear all interrupts */
421         writel(0xffffffff, &dv_aintc_regs->fiq0);
422         writel(0xffffffff, &dv_aintc_regs->fiq1);
423         writel(0xffffffff, &dv_aintc_regs->irq0);
424         writel(0xffffffff, &dv_aintc_regs->irq1);
425
426         dm365_por_reset();
427         dm365_wdt_reset();
428
429         /* System PSC setup - enable all */
430         dm365_psc_init();
431
432         /* Setup Pinmux */
433         dm365_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX0);
434         dm365_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX1);
435         dm365_pinmux_ctl(2, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX2);
436         dm365_pinmux_ctl(3, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX3);
437         dm365_pinmux_ctl(4, 0xFFFFFFFF, CONFIG_SYS_DM36x_PINMUX4);
438
439         /* PLL setup */
440         dm365_pll1_init(CONFIG_SYS_DM36x_PLL1_PLLM,
441                 CONFIG_SYS_DM36x_PLL1_PREDIV);
442         dm365_pll2_init(CONFIG_SYS_DM36x_PLL2_PLLM,
443                 CONFIG_SYS_DM36x_PLL2_PREDIV);
444
445         /* GPIO setup */
446         board_gpio_init();
447
448         NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
449                         CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
450
451         /*
452          * Fix Power and Emulation Management Register
453          * see sprufh2.pdf page 38 Table 22
454          */
455         writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
456                 DAVINCI_UART_PWREMU_MGMT_UTRST),
457                &davinci_uart_ctrl_regs->pwremu_mgmt);
458
459         puts("ddr init\n");
460         dm365_ddr_setup();
461
462         puts("emif init\n");
463         dm365_emif_init();
464
465         dm365_wdt_flag_on();
466
467 #if defined(CONFIG_POST)
468         /*
469          * Do memory tests, calls arch_memory_failure_handle()
470          * if error detected.
471          */
472         memory_post_test(0);
473 #endif
474 }