2 * Low-level board setup code for TI DaVinci SoC based boards.
4 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * Partially based on TI sources, original copyrights follow:
10 * Board specific setup info
13 * Texas Instruments, <www.ti.com>
14 * Kshitij Gupta <Kshitij@ti.com>
16 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
18 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
19 * See file CREDITS for list of people who contributed to this
22 * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
23 * See file CREDITS for list of people who contributed to this
26 * Modified for DV-EVM board by Swaminathan S, Nov 2005
27 * See file CREDITS for list of people who contributed to this
30 * This program is free software; you can redistribute it and/or
31 * modify it under the terms of the GNU General Public License as
32 * published by the Free Software Foundation; either version 2 of
33 * the License, or (at your option) any later version.
35 * This program is distributed in the hope that it will be useful,
36 * but WITHOUT ANY WARRANTY; without even the implied warranty of
37 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
38 * GNU General Public License for more details.
40 * You should have received a copy of the GNU General Public License
41 * along with this program; if not, write to the Free Software
42 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
48 #define MDSTAT_STATE 0x3f
52 #ifdef CONFIG_SOC_DM644X
54 /*-------------------------------------------------------*
55 * Mask all IRQs by setting all bits in the EINT default *
56 *-------------------------------------------------------*/
63 /*------------------------------------------------------*
64 * Put the GEM in reset *
65 *------------------------------------------------------*/
67 /* Put the GEM in reset */
68 ldr r8, PSC_GEM_FLAG_CLEAR
74 /* Enable the Power Domain Transition Command */
80 /* Check for Transition Complete(PTSTAT) */
85 bne checkStatClkStopGem
87 /* Check for GEM Reset Completion */
92 bne checkGemStatClkStop
94 /* Do this for enabling a WDT initiated reset this is a workaround
95 for a chip bug. Not required under normal situations */
100 /*------------------------------------------------------*
101 * Enable L1 & L2 Memories in Fast mode *
102 *------------------------------------------------------*/
108 ldr r10, MMARG_BRF0_VAL
115 /*------------------------------------------------------*
116 * DDR2 PLL Initialization *
117 *------------------------------------------------------*/
119 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
122 ldr r7, PLL_CLKSRC_MASK
129 /* Select the PLLEN source */
130 ldr r7, PLL_ENSRC_MASK
135 ldr r7, PLL_BYPASS_MASK
139 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
146 ldr r7, PLL_RESET_MASK
150 /* Power up the PLL */
151 ldr r7, PLL_PWRUP_MASK
155 /* Enable the PLL from Disable Mode */
156 ldr r7, PLL_DISABLE_ENABLE_MASK
160 /* Program the PLL Multiplier */
162 mov r2, $0x17 /* 162 MHz */
165 /* Program the PLL2 Divisor Value */
170 /* Program the PLL2 Divisor Value */
172 mov r4, $0x0b /* 54 MHz */
176 ldr r8, PLL2_DIV_MASK
185 /* Program the GOSET bit to take new divider values */
199 ldr r8, PLL2_DIV_MASK
208 /* Program the GOSET bit to take new divider values */
221 /* Wait for PLL to Reset Properly */
227 /* Bring PLL out of Reset */
233 /* Wait for PLL to Lock */
234 ldr r10, PLL_LOCK_COUNT
245 /*------------------------------------------------------*
246 * Issue Soft Reset to DDR Module *
247 *------------------------------------------------------*/
249 /* Shut down the DDR2 LPSC Module */
250 ldr r8, PSC_FLAG_CLEAR
257 /* Enable the Power Domain Transition Command */
263 /* Check for Transition Complete(PTSTAT) */
270 /* Check for DDR2 Controller Enable Completion */
274 and r7, r7, $MDSTAT_STATE
276 bne checkDDRStatClkStop
278 /*------------------------------------------------------*
279 * Program DDR2 MMRs for 162MHz Setting *
280 *------------------------------------------------------*/
282 /* Program PHY Control Register */
287 /* Program SDRAM Bank Config Register */
292 /* Program SDRAM TIM-0 Config Register */
294 ldr r7, SDTIM0_VAL_162MHz
297 /* Program SDRAM TIM-1 Config Register */
299 ldr r7, SDTIM1_VAL_162MHz
302 /* Program the SDRAM Bank Config Control Register */
309 /* Program SDRAM SDREF Config Register */
314 /*------------------------------------------------------*
315 * Issue Soft Reset to DDR Module *
316 *------------------------------------------------------*/
318 /* Issue a Dummy DDR2 read/write */
319 ldr r8, DDR2_START_ADDR
324 /* Shut down the DDR2 LPSC Module */
325 ldr r8, PSC_FLAG_CLEAR
332 /* Enable the Power Domain Transition Command */
338 /* Check for Transition Complete(PTSTAT) */
343 bne checkStatClkStop2
345 /* Check for DDR2 Controller Enable Completion */
346 checkDDRStatClkStop2:
349 and r7, r7, $MDSTAT_STATE
351 bne checkDDRStatClkStop2
353 /*------------------------------------------------------*
354 * Turn DDR2 Controller Clocks On *
355 *------------------------------------------------------*/
357 /* Enable the DDR2 LPSC Module */
363 /* Enable the Power Domain Transition Command */
369 /* Check for Transition Complete(PTSTAT) */
376 /* Check for DDR2 Controller Enable Completion */
380 and r7, r7, $MDSTAT_STATE
382 bne checkDDRStatClkEn2
384 /* DDR Writes and Reads */
389 /*------------------------------------------------------*
390 * System PLL Initialization *
391 *------------------------------------------------------*/
393 /* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
396 ldr r7, PLL_CLKSRC_MASK
403 /* Select the PLLEN source */
404 ldr r7, PLL_ENSRC_MASK
409 ldr r7, PLL_BYPASS_MASK
413 /* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
421 ldr r7, PLL_RESET_MASK
425 /* Disable the PLL */
429 /* Power up the PLL */
430 ldr r7, PLL_PWRUP_MASK
434 /* Enable the PLL from Disable Mode */
435 ldr r7, PLL_DISABLE_ENABLE_MASK
439 /* Program the PLL Multiplier */
441 mov r3, $0x15 /* For 594MHz */
444 /* Wait for PLL to Reset Properly */
451 /* Bring PLL out of Reset */
456 /* Wait for PLL to Lock */
457 ldr r10, PLL_LOCK_COUNT
472 /*------------------------------------------------------*
473 * AEMIF configuration for NOR Flash (double check) *
474 *------------------------------------------------------*/
503 /*--------------------------------------*
504 * VTP manual Calibration *
505 *--------------------------------------*/
514 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
515 ldr r10, VTP_LOCK_COUNT
526 mov r8, r7, LSL #32-10
527 mov r8, r8, LSR #32-10 /* grab low 10 bits */
535 /* Wait for 33 VTP CLK cycles. VRP operates at 27 MHz */
536 ldr r10, VTP_LOCK_COUNT
551 * Call board-specific lowlevel init.
552 * That MUST be present and THAT returns
553 * back to arch calling code with "mov pc, lr."
560 .word 0x01c40000 /* Device Configuration Registers */
562 .word 0x01c40004 /* Device Configuration Registers */
604 /* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
618 #elif defined DDR_8BANKS
621 #error "Unknown DDR configuration!!!"
632 .word 0x200000f0 /* VTP IO Control register */
634 .word 0x01c42030 /* DDR VPTR MMR */
654 /* GEM Power Up & LPSC Control Register */
660 /* For WDT reset chip bug */
665 .word 0xfffffeff /* Mask the Clock Mode bit */
667 .word 0xffffffdf /* Select the PLLEN source */
669 .word 0xfffffffe /* Put the PLL in BYPASS */
671 .word 0xfffffff7 /* Put the PLL in Reset Mode */
673 .word 0xfffffffd /* PLL Power up Mask Bit */
674 PLL_DISABLE_ENABLE_MASK:
675 .word 0xffffffef /* Enable the PLL from Disable */
679 /* PLL1-SYSTEM PLL MMRs */
685 /* PLL2-SYSTEM PLL MMRs */
702 .word 0x01c42010 /* BRF margin mode 0 (R/W)*/
710 #else /* CONFIG_SOC_DM644X */