3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/cache.h>
12 #include <u-boot/md5.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/kirkwood.h>
19 void reset_cpu(unsigned long ignored)
21 struct kwcpu_registers *cpureg =
22 (struct kwcpu_registers *)KW_CPU_REG_BASE;
24 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
25 &cpureg->rstoutn_mask);
26 writel(readl(&cpureg->sys_soft_rst) | 1,
27 &cpureg->sys_soft_rst);
32 * Generates Ramdom hex number reading some time varient system registers
33 * and using md5 algorithm
35 unsigned char get_random_hex(void)
42 * in case of 88F6281/88F6282/88F6192 A0,
43 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
44 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
45 * reserved regs and does not have names at this moment
46 * (no errata available)
48 writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
49 for (i = 0; i < BUFLEN; i++) {
50 inbuf[i] = readl(KW_REG_UNDOC_0x1470);
52 md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
53 return outbuf[outbuf[7] % 0x0f];
58 * Used with the Base register to set the address window size and location.
59 * Must be programmed from LSB to MSB as sequence of ones followed by
60 * sequence of zeros. The number of ones specifies the size of the window in
61 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
62 * NOTE: A value of 0x0 specifies 64-KByte size.
64 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
68 u32 val = sizeval >> 1;
70 for (i = 0; val >= 0x10000; i++) {
74 return (0x0000ffff & j);
78 * kw_config_adr_windows - Configure address Windows
80 * There are 8 address windows supported by Kirkwood Soc to addess different
81 * devices. Each window can be configured for size, BAR and remap addr
82 * Below configuration is standard for most of the cases
84 * If remap function not used, remap_lo must be set as base
86 * Reference Documentation:
87 * Mbus-L to Mbus Bridge Registers Configuration.
88 * (Sec 25.1 and 25.3 of Datasheet)
90 int kw_config_adr_windows(void)
92 struct kwwin_registers *winregs =
93 (struct kwwin_registers *)KW_CPU_WIN_BASE;
95 /* Window 0: PCIE MEM address space */
96 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
97 KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
99 writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
100 writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
101 writel(0x0, &winregs[0].remap_hi);
103 /* Window 1: PCIE IO address space */
104 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
105 KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
106 writel(KW_DEFADR_PCI_IO, &winregs[1].base);
107 writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
108 writel(0x0, &winregs[1].remap_hi);
110 /* Window 2: NAND Flash address space */
111 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
112 KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
113 writel(KW_DEFADR_NANDF, &winregs[2].base);
114 writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
115 writel(0x0, &winregs[2].remap_hi);
117 /* Window 3: SPI Flash address space */
118 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
119 KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
120 writel(KW_DEFADR_SPIF, &winregs[3].base);
121 writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
122 writel(0x0, &winregs[3].remap_hi);
124 /* Window 4: BOOT Memory address space */
125 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
126 KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
127 writel(KW_DEFADR_BOOTROM, &winregs[4].base);
129 /* Window 5: Security SRAM address space */
130 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
131 KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
132 writel(KW_DEFADR_SASRAM, &winregs[5].base);
134 /* Window 6-7: Disabled */
135 writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
136 writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
142 * kw_config_gpio - GPIO configuration
144 void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
146 struct kwgpio_registers *gpio0reg =
147 (struct kwgpio_registers *)KW_GPIO0_BASE;
148 struct kwgpio_registers *gpio1reg =
149 (struct kwgpio_registers *)KW_GPIO1_BASE;
151 /* Init GPIOS to default values as per board requirement */
152 writel(gpp0_oe_val, &gpio0reg->dout);
153 writel(gpp1_oe_val, &gpio1reg->dout);
154 writel(gpp0_oe, &gpio0reg->oe);
155 writel(gpp1_oe, &gpio1reg->oe);
159 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
161 * Each MPP can be configured to different functionality through
162 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
164 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
165 * Each MPP functionality can be configuration by a 4bit value
166 * of MPP control reg, the value and associated functionality depends
167 * upon used SoC varient
169 int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
170 u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
172 u32 *mppreg = (u32 *) KW_MPP_BASE;
174 /* program mpp registers */
175 writel(mpp0_7, &mppreg[0]);
176 writel(mpp8_15, &mppreg[1]);
177 writel(mpp16_23, &mppreg[2]);
178 writel(mpp24_31, &mppreg[3]);
179 writel(mpp32_39, &mppreg[4]);
180 writel(mpp40_47, &mppreg[5]);
181 writel(mpp48_55, &mppreg[6]);
186 * SYSRSTn Duration Counter Support
188 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
189 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
190 * The SYSRSTn duration counter is useful for implementing a manufacturer
191 * or factory reset. Upon a long reset assertion that is greater than a
192 * pre-configured environment variable value for sysrstdelay,
193 * The counter value is stored in the SYSRSTn Length Counter Register
194 * The counter is based on the 25-MHz reference clock (40ns)
195 * It is a 29-bit counter, yielding a maximum counting duration of
196 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
197 * it remains at this value until counter reset is triggered by setting
198 * bit 31 of KW_REG_SYSRST_CNT
200 static void kw_sysrst_action(void)
203 char *s = getenv("sysrstcmd");
206 debug("Error.. %s failed, check sysrstcmd\n",
211 debug("Starting %s process...\n", __FUNCTION__);
212 ret = run_command(s, 0);
214 debug("Error.. %s failed\n", __FUNCTION__);
216 debug("%s process finished\n", __FUNCTION__);
219 static void kw_sysrst_check(void)
221 u32 sysrst_cnt, sysrst_dly;
225 * no action if sysrstdelay environment variable is not defined
227 s = getenv("sysrstdelay");
231 /* read sysrstdelay value */
232 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
234 /* read SysRst Length counter register (bits 28:0) */
235 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
236 debug("H/w Rst hold time: %d.%d secs\n",
237 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
238 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
240 /* clear the counter for next valid read*/
241 writel(1 << 31, KW_REG_SYSRST_CNT);
245 * if H/w Reset key is pressed and hold for time
246 * more than sysrst_dly in seconds
248 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
252 #if defined(CONFIG_DISPLAY_CPUINFO)
253 int print_cpuinfo(void)
256 u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
257 u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
259 if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
260 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
279 printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
282 #endif /* CONFIG_DISPLAY_CPUINFO */
284 #ifdef CONFIG_ARCH_CPU_INIT
285 int arch_cpu_init(void)
288 struct kwcpu_registers *cpureg =
289 (struct kwcpu_registers *)KW_CPU_REG_BASE;
291 /* Linux expects` the internal registers to be at 0xf1000000 */
292 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
294 /* Enable and invalidate L2 cache in write through mode */
295 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
296 invalidate_l2_cache();
298 kw_config_adr_windows();
300 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
302 * Configures the I/O voltage of the pads connected to Egigabit
303 * Ethernet interface to 1.8V
304 * By default it is set to 3.3V
306 reg = readl(KW_REG_MPP_OUT_DRV_REG);
308 writel(reg, KW_REG_MPP_OUT_DRV_REG);
310 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
312 * Set egiga port0/1 in normal functional mode
313 * This is required becasue on kirkwood by default ports are in reset mode
314 * OS egiga driver may not have provision to set them in normal mode
315 * and if u-boot is build without network support, network may fail at OS level
317 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
318 reg &= ~(1 << 4); /* Clear PortReset Bit */
319 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
320 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
321 reg &= ~(1 << 4); /* Clear PortReset Bit */
322 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
324 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
326 * Enable PCI Express Port0
328 reg = readl(&cpureg->ctrl_stat);
329 reg |= (1 << 0); /* Set PEX0En Bit */
330 writel(reg, &cpureg->ctrl_stat);
334 #endif /* CONFIG_ARCH_CPU_INIT */
337 * SOC specific misc init
339 #if defined(CONFIG_ARCH_MISC_INIT)
340 int arch_misc_init(void)
344 /*CPU streaming & write allocate */
345 temp = readfr_extra_feature_reg();
346 temp &= ~(1 << 28); /* disable wr alloc */
347 writefr_extra_feature_reg(temp);
349 temp = readfr_extra_feature_reg();
350 temp &= ~(1 << 29); /* streaming disabled */
351 writefr_extra_feature_reg(temp);
353 /* L2Cache settings */
354 temp = readfr_extra_feature_reg();
355 /* Disable L2C pre fetch - Set bit 24 */
357 /* enable L2C - Set bit 22 */
359 writefr_extra_feature_reg(temp);
362 /* Change reset vector to address 0x0 */
364 set_cr(temp & ~CR_V);
366 /* checks and execute resset to factory event */
371 #endif /* CONFIG_ARCH_MISC_INIT */
374 int cpu_eth_init(bd_t *bis)
376 mvgbe_initialize(bis);