3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
27 #include <asm/cache.h>
28 #include <u-boot/md5.h>
30 #include <asm/arch/cpu.h>
31 #include <asm/arch/kirkwood.h>
36 void reset_cpu(unsigned long ignored)
38 struct kwcpu_registers *cpureg =
39 (struct kwcpu_registers *)KW_CPU_REG_BASE;
41 writel(readl(&cpureg->rstoutn_mask) | (1 << 2),
42 &cpureg->rstoutn_mask);
43 writel(readl(&cpureg->sys_soft_rst) | 1,
44 &cpureg->sys_soft_rst);
49 * Generates Ramdom hex number reading some time varient system registers
50 * and using md5 algorithm
52 unsigned char get_random_hex(void)
59 * in case of 88F6281/88F6282/88F6192 A0,
60 * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
61 * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
62 * reserved regs and does not have names at this moment
63 * (no errata available)
65 writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
66 for (i = 0; i < BUFLEN; i++) {
67 inbuf[i] = readl(KW_REG_UNDOC_0x1470);
69 md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
70 return outbuf[outbuf[7] % 0x0f];
75 * Used with the Base register to set the address window size and location.
76 * Must be programmed from LSB to MSB as sequence of ones followed by
77 * sequence of zeros. The number of ones specifies the size of the window in
78 * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte).
79 * NOTE: A value of 0x0 specifies 64-KByte size.
81 unsigned int kw_winctrl_calcsize(unsigned int sizeval)
85 u32 val = sizeval >> 1;
87 for (i = 0; val >= 0x10000; i++) {
91 return (0x0000ffff & j);
95 * kw_config_adr_windows - Configure address Windows
97 * There are 8 address windows supported by Kirkwood Soc to addess different
98 * devices. Each window can be configured for size, BAR and remap addr
99 * Below configuration is standard for most of the cases
101 * If remap function not used, remap_lo must be set as base
103 * Reference Documentation:
104 * Mbus-L to Mbus Bridge Registers Configuration.
105 * (Sec 25.1 and 25.3 of Datasheet)
107 int kw_config_adr_windows(void)
109 struct kwwin_registers *winregs =
110 (struct kwwin_registers *)KW_CPU_WIN_BASE;
112 /* Window 0: PCIE MEM address space */
113 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE,
114 KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl);
116 writel(KW_DEFADR_PCI_MEM, &winregs[0].base);
117 writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo);
118 writel(0x0, &winregs[0].remap_hi);
120 /* Window 1: PCIE IO address space */
121 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE,
122 KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl);
123 writel(KW_DEFADR_PCI_IO, &winregs[1].base);
124 writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo);
125 writel(0x0, &winregs[1].remap_hi);
127 /* Window 2: NAND Flash address space */
128 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
129 KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl);
130 writel(KW_DEFADR_NANDF, &winregs[2].base);
131 writel(KW_DEFADR_NANDF, &winregs[2].remap_lo);
132 writel(0x0, &winregs[2].remap_hi);
134 /* Window 3: SPI Flash address space */
135 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
136 KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl);
137 writel(KW_DEFADR_SPIF, &winregs[3].base);
138 writel(KW_DEFADR_SPIF, &winregs[3].remap_lo);
139 writel(0x0, &winregs[3].remap_hi);
141 /* Window 4: BOOT Memory address space */
142 writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY,
143 KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl);
144 writel(KW_DEFADR_BOOTROM, &winregs[4].base);
146 /* Window 5: Security SRAM address space */
147 writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM,
148 KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl);
149 writel(KW_DEFADR_SASRAM, &winregs[5].base);
151 /* Window 6-7: Disabled */
152 writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl);
153 writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl);
159 * kw_config_gpio - GPIO configuration
161 void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
163 struct kwgpio_registers *gpio0reg =
164 (struct kwgpio_registers *)KW_GPIO0_BASE;
165 struct kwgpio_registers *gpio1reg =
166 (struct kwgpio_registers *)KW_GPIO1_BASE;
168 /* Init GPIOS to default values as per board requirement */
169 writel(gpp0_oe_val, &gpio0reg->dout);
170 writel(gpp1_oe_val, &gpio1reg->dout);
171 writel(gpp0_oe, &gpio0reg->oe);
172 writel(gpp1_oe, &gpio1reg->oe);
176 * kw_config_mpp - Multi-Purpose Pins Functionality configuration
178 * Each MPP can be configured to different functionality through
179 * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
181 * There are maximum 64 Multi-Pourpose Pins on Kirkwood
182 * Each MPP functionality can be configuration by a 4bit value
183 * of MPP control reg, the value and associated functionality depends
184 * upon used SoC varient
186 int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
187 u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
189 u32 *mppreg = (u32 *) KW_MPP_BASE;
191 /* program mpp registers */
192 writel(mpp0_7, &mppreg[0]);
193 writel(mpp8_15, &mppreg[1]);
194 writel(mpp16_23, &mppreg[2]);
195 writel(mpp24_31, &mppreg[3]);
196 writel(mpp32_39, &mppreg[4]);
197 writel(mpp40_47, &mppreg[5]);
198 writel(mpp48_55, &mppreg[6]);
203 * SYSRSTn Duration Counter Support
205 * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
206 * When SYSRSTn is asserted low, a SYSRSTn duration counter is running.
207 * The SYSRSTn duration counter is useful for implementing a manufacturer
208 * or factory reset. Upon a long reset assertion that is greater than a
209 * pre-configured environment variable value for sysrstdelay,
210 * The counter value is stored in the SYSRSTn Length Counter Register
211 * The counter is based on the 25-MHz reference clock (40ns)
212 * It is a 29-bit counter, yielding a maximum counting duration of
213 * 2^29/25 MHz (21.4 seconds). When the counter reach its maximum value,
214 * it remains at this value until counter reset is triggered by setting
215 * bit 31 of KW_REG_SYSRST_CNT
217 static void kw_sysrst_action(void)
220 char *s = getenv("sysrstcmd");
223 debug("Error.. %s failed, check sysrstcmd\n",
228 debug("Starting %s process...\n", __FUNCTION__);
229 ret = run_command(s, 0);
231 debug("Error.. %s failed\n", __FUNCTION__);
233 debug("%s process finished\n", __FUNCTION__);
236 static void kw_sysrst_check(void)
238 u32 sysrst_cnt, sysrst_dly;
242 * no action if sysrstdelay environment variable is not defined
244 s = getenv("sysrstdelay");
248 /* read sysrstdelay value */
249 sysrst_dly = (u32) simple_strtoul(s, NULL, 10);
251 /* read SysRst Length counter register (bits 28:0) */
252 sysrst_cnt = (0x1fffffff & readl(KW_REG_SYSRST_CNT));
253 debug("H/w Rst hold time: %d.%d secs\n",
254 sysrst_cnt / SYSRST_CNT_1SEC_VAL,
255 sysrst_cnt % SYSRST_CNT_1SEC_VAL);
257 /* clear the counter for next valid read*/
258 writel(1 << 31, KW_REG_SYSRST_CNT);
262 * if H/w Reset key is pressed and hold for time
263 * more than sysrst_dly in seconds
265 if (sysrst_cnt >= SYSRST_CNT_1SEC_VAL * sysrst_dly)
269 #if defined(CONFIG_DISPLAY_CPUINFO)
270 int print_cpuinfo(void)
273 u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
274 u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
276 if ((readl(KW_REG_DEVICE_ID) & 0x03) > 2) {
277 printf("Error.. %s:Unsupported Kirkwood SoC 88F%04x\n", __FUNCTION__, devid);
296 printf("SoC: Kirkwood 88F%04x_%s\n", devid, rev);
299 #endif /* CONFIG_DISPLAY_CPUINFO */
301 #ifdef CONFIG_ARCH_CPU_INIT
302 int arch_cpu_init(void)
305 struct kwcpu_registers *cpureg =
306 (struct kwcpu_registers *)KW_CPU_REG_BASE;
308 /* Linux expects` the internal registers to be at 0xf1000000 */
309 writel(KW_REGS_PHY_BASE, KW_OFFSET_REG);
311 /* Enable and invalidate L2 cache in write through mode */
312 writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg);
313 invalidate_l2_cache();
315 kw_config_adr_windows();
317 #ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8
319 * Configures the I/O voltage of the pads connected to Egigabit
320 * Ethernet interface to 1.8V
321 * By defult it is set to 3.3V
323 reg = readl(KW_REG_MPP_OUT_DRV_REG);
325 writel(reg, KW_REG_MPP_OUT_DRV_REG);
327 #ifdef CONFIG_KIRKWOOD_EGIGA_INIT
329 * Set egiga port0/1 in normal functional mode
330 * This is required becasue on kirkwood by default ports are in reset mode
331 * OS egiga driver may not have provision to set them in normal mode
332 * and if u-boot is build without network support, network may fail at OS level
334 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0));
335 reg &= ~(1 << 4); /* Clear PortReset Bit */
336 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0)));
337 reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1));
338 reg &= ~(1 << 4); /* Clear PortReset Bit */
339 writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1)));
341 #ifdef CONFIG_KIRKWOOD_PCIE_INIT
343 * Enable PCI Express Port0
345 reg = readl(&cpureg->ctrl_stat);
346 reg |= (1 << 0); /* Set PEX0En Bit */
347 writel(reg, &cpureg->ctrl_stat);
351 #endif /* CONFIG_ARCH_CPU_INIT */
354 * SOC specific misc init
356 #if defined(CONFIG_ARCH_MISC_INIT)
357 int arch_misc_init(void)
361 /*CPU streaming & write allocate */
362 temp = readfr_extra_feature_reg();
363 temp &= ~(1 << 28); /* disable wr alloc */
364 writefr_extra_feature_reg(temp);
366 temp = readfr_extra_feature_reg();
367 temp &= ~(1 << 29); /* streaming disabled */
368 writefr_extra_feature_reg(temp);
370 /* L2Cache settings */
371 temp = readfr_extra_feature_reg();
372 /* Disable L2C pre fetch - Set bit 24 */
374 /* enable L2C - Set bit 22 */
376 writefr_extra_feature_reg(temp);
379 /* Change reset vector to address 0x0 */
381 set_cr(temp & ~CR_V);
383 /* checks and execute resset to factory event */
388 #endif /* CONFIG_ARCH_MISC_INIT */
391 int cpu_eth_init(bd_t *bis)
393 mvgbe_initialize(bis);