3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 #include <asm/arch/cpu.h>
29 #include <asm/arch/kirkwood.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 struct kw_sdram_bank {
38 struct kw_sdram_addr_dec {
39 struct kw_sdram_bank sdram_bank[4];
42 #define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
43 #define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
44 #define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
45 #define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
48 * kw_sdram_bar - reads SDRAM Base Address Register
50 u32 kw_sdram_bar(enum memory_bank bank)
52 struct kw_sdram_addr_dec *base =
53 (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
55 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
57 if ((!enable) || (bank > BANK3))
60 result = readl(&base->sdram_bank[bank].win_bar);
65 * kw_sdram_bs_set - writes SDRAM Bank size
67 static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
69 struct kw_sdram_addr_dec *base =
70 (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
71 /* Read current register value */
72 u32 reg = readl(&base->sdram_bank[bank].win_sz);
74 /* Clear window size */
75 reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
77 /* Set new window size */
78 reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
80 writel(reg, &base->sdram_bank[bank].win_sz);
84 * kw_sdram_bs - reads SDRAM Bank size
86 u32 kw_sdram_bs(enum memory_bank bank)
88 struct kw_sdram_addr_dec *base =
89 (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
91 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
93 if ((!enable) || (bank > BANK3))
95 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
100 void kw_sdram_size_adjust(enum memory_bank bank)
104 /* probe currently equipped RAM size */
105 size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
107 /* adjust SDRAM window size accordingly */
108 kw_sdram_bs_set(bank, size);
111 #ifndef CONFIG_SYS_BOARD_DRAM_INIT
117 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
118 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
119 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
121 * It is assumed that all memory banks are consecutive
123 * If the gap is found, ram_size will be reported for
124 * consecutive memory only
126 if (gd->bd->bi_dram[i].start != gd->ram_size)
129 gd->ram_size += gd->bd->bi_dram[i].size;
133 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
134 /* If above loop terminated prematurely, we need to set
135 * remaining banks' start address & size as 0. Otherwise other
136 * u-boot functions and Linux kernel gets wrong values which
137 * could result in crash */
138 gd->bd->bi_dram[i].start = 0;
139 gd->bd->bi_dram[i].size = 0;
146 * If this function is not defined here,
147 * board.c alters dram bank zero configuration defined above.
149 void dram_init_banksize(void)
153 #endif /* CONFIG_SYS_BOARD_DRAM_INIT */