3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/cpu.h>
13 #include <asm/arch/kirkwood.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 struct kw_sdram_bank {
22 struct kw_sdram_addr_dec {
23 struct kw_sdram_bank sdram_bank[4];
26 #define KW_REG_CPUCS_WIN_ENABLE (1 << 0)
27 #define KW_REG_CPUCS_WIN_WR_PROTECT (1 << 1)
28 #define KW_REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
29 #define KW_REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
32 * kw_sdram_bar - reads SDRAM Base Address Register
34 u32 kw_sdram_bar(enum memory_bank bank)
36 struct kw_sdram_addr_dec *base =
37 (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
39 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
41 if ((!enable) || (bank > BANK3))
44 result = readl(&base->sdram_bank[bank].win_bar);
49 * kw_sdram_bs_set - writes SDRAM Bank size
51 static void kw_sdram_bs_set(enum memory_bank bank, u32 size)
53 struct kw_sdram_addr_dec *base =
54 (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
55 /* Read current register value */
56 u32 reg = readl(&base->sdram_bank[bank].win_sz);
58 /* Clear window size */
59 reg &= ~KW_REG_CPUCS_WIN_SIZE(0xFF);
61 /* Set new window size */
62 reg |= KW_REG_CPUCS_WIN_SIZE((size - 1) >> 24);
64 writel(reg, &base->sdram_bank[bank].win_sz);
68 * kw_sdram_bs - reads SDRAM Bank size
70 u32 kw_sdram_bs(enum memory_bank bank)
72 struct kw_sdram_addr_dec *base =
73 (struct kw_sdram_addr_dec *)KW_REGISTER(0x1500);
75 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
77 if ((!enable) || (bank > BANK3))
79 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
84 void kw_sdram_size_adjust(enum memory_bank bank)
88 /* probe currently equipped RAM size */
89 size = get_ram_size((void *)kw_sdram_bar(bank), kw_sdram_bs(bank));
91 /* adjust SDRAM window size accordingly */
92 kw_sdram_bs_set(bank, size);
95 #ifndef CONFIG_SYS_BOARD_DRAM_INIT
101 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
102 gd->bd->bi_dram[i].start = kw_sdram_bar(i);
103 gd->bd->bi_dram[i].size = kw_sdram_bs(i);
105 * It is assumed that all memory banks are consecutive
107 * If the gap is found, ram_size will be reported for
108 * consecutive memory only
110 if (gd->bd->bi_dram[i].start != gd->ram_size)
113 gd->ram_size += gd->bd->bi_dram[i].size;
117 for (; i < CONFIG_NR_DRAM_BANKS; i++) {
118 /* If above loop terminated prematurely, we need to set
119 * remaining banks' start address & size as 0. Otherwise other
120 * u-boot functions and Linux kernel gets wrong values which
121 * could result in crash */
122 gd->bd->bi_dram[i].start = 0;
123 gd->bd->bi_dram[i].size = 0;
130 * If this function is not defined here,
131 * board.c alters dram bank zero configuration defined above.
133 void dram_init_banksize(void)
137 #endif /* CONFIG_SYS_BOARD_DRAM_INIT */