2 * Copyright (C) Marvell International Ltd. and its affiliates
3 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <asm/arch/kirkwood.h>
28 #define UBOOT_CNTR 0 /* counter to use for uboot timer */
30 /* Timer reload and current value registers */
32 u32 reload; /* Timer reload reg */
33 u32 val; /* Timer value reg */
37 struct kwtmr_registers {
38 u32 ctrl; /* Timer control reg */
40 struct kwtmr_val tmr[2];
45 struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE;
48 * ARM Timers Registers Map
50 #define CNTMR_CTRL_REG &kwtmr_regs->ctrl
51 #define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload
52 #define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val
55 * ARM Timers Control Register
56 * CPU_TIMERS_CTRL_REG (CTCR)
58 #define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
59 #define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS)
60 #define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
61 #define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr))
63 #define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
64 #define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1)
65 #define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
66 #define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
69 * ARM Timer\Watchdog Reload Register
70 * CNTMR_RELOAD_REG (TRR)
72 #define TRG_ARM_TIMER_REL_OFFS 0
73 #define TRG_ARM_TIMER_REL_MASK 0xffffffff
76 * ARM Timer\Watchdog Register
77 * CNTMR_VAL_REG (TVRG)
79 #define TVR_ARM_TIMER_OFFS 0
80 #define TVR_ARM_TIMER_MASK 0xffffffff
81 #define TVR_ARM_TIMER_MAX 0xffffffff
82 #define TIMER_LOAD_VAL 0xffffffff
84 #define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \
85 (CONFIG_SYS_TCLK / 1000))
87 DECLARE_GLOBAL_DATA_PTR;
89 #define timestamp gd->tbl
90 #define lastdec gd->lastinc
92 ulong get_timer_masked(void)
94 ulong now = READ_TIMER;
98 timestamp += lastdec - now;
100 /* we have an overflow ... */
101 timestamp += lastdec +
102 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
109 ulong get_timer(ulong base)
111 return get_timer_masked() - base;
114 void __udelay(unsigned long usec)
119 current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
120 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
122 if (current < delayticks) {
123 delayticks -= current;
124 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
125 while ((TIMER_LOAD_VAL - delayticks) <
126 readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
128 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
129 (current - delayticks)) ;
138 unsigned int cntmrctrl;
140 /* load value into timer */
141 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
142 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
144 /* enable timer in auto reload mode */
145 cntmrctrl = readl(CNTMR_CTRL_REG);
146 cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR);
147 cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR);
148 writel(cntmrctrl, CNTMR_CTRL_REG);
150 /* init the timestamp and lastdec value */
151 lastdec = READ_TIMER;
158 * This function is derived from PowerPC code (read timebase as long long).
159 * On ARM it just returns the timer value.
161 unsigned long long get_ticks(void)
167 * This function is derived from PowerPC code (timebase clock frequency).
168 * On ARM it returns the number of timer ticks per second.
170 ulong get_tbclk (void)
172 return (ulong)CONFIG_SYS_HZ;