2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/clk.h>
13 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
15 unsigned int get_sys_clk_rate(void)
17 if (readl(&clk->sysclk_ctrl) & CLK_SYSCLK_PLL397)
18 return RTC_CLK_FREQUENCY * 397;
20 return OSC_CLK_FREQUENCY;
23 unsigned int get_hclk_pll_rate(void)
25 unsigned long long fin, fref, fcco, fout;
26 u32 val, m_div, n_div, p_div;
29 * Valid frequency ranges:
30 * 1 * 10^6 <= Fin <= 20 * 10^6
31 * 1 * 10^6 <= Fref <= 27 * 10^6
32 * 156 * 10^6 <= Fcco <= 320 * 10^6
35 fref = fin = get_sys_clk_rate();
36 if (fin > 20000000ULL || fin < 1000000ULL)
39 val = readl(&clk->hclkpll_ctrl);
40 m_div = ((val & CLK_HCLK_PLL_FEEDBACK_DIV_MASK) >> 1) + 1;
41 n_div = ((val & CLK_HCLK_PLL_PREDIV_MASK) >> 9) + 1;
42 if (val & CLK_HCLK_PLL_DIRECT)
45 p_div = ((val & CLK_HCLK_PLL_POSTDIV_MASK) >> 11) + 1;
48 if (val & CLK_HCLK_PLL_BYPASS) {
54 if (fref > 27000000ULL || fref < 1000000ULL)
58 if (val & CLK_HCLK_PLL_FEEDBACK) {
64 if (fcco > 320000000ULL || fcco < 156000000ULL)
70 unsigned int get_hclk_clk_div(void)
74 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK;
79 unsigned int get_hclk_clk_rate(void)
81 return get_hclk_pll_rate() / get_hclk_clk_div();
84 unsigned int get_periph_clk_div(void)
88 val = readl(&clk->hclkdiv_ctrl) & CLK_HCLK_PERIPH_DIV_MASK;
90 return (val >> 2) + 1;
93 unsigned int get_periph_clk_rate(void)
95 if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
96 return get_sys_clk_rate();
98 return get_hclk_pll_rate() / get_periph_clk_div();
101 unsigned int get_sdram_clk_rate(void)
103 unsigned int src_clk;
105 if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN))
106 return get_sys_clk_rate();
108 src_clk = get_hclk_pll_rate();
110 if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) {
112 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) {
113 case CLK_HCLK_DDRAM_HALF:
115 case CLK_HCLK_DDRAM_NOMINAL:
122 switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) {
123 case CLK_HCLK_ARM_PLL_DIV_4:
125 case CLK_HCLK_ARM_PLL_DIV_2:
127 case CLK_HCLK_ARM_PLL_DIV_1:
135 int get_serial_clock(void)
137 return get_periph_clk_rate();