2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arch/cpu.h>
9 #include <asm/arch/clk.h>
10 #include <asm/arch/wdt.h>
13 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
14 static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
16 void reset_cpu(ulong addr)
18 /* Enable watchdog clock */
19 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
21 /* Reset pulse length is 13005 peripheral clock frames */
22 writel(13000, &wdt->pulse);
24 /* Force WDOG_RESET2 and RESOUT_N signal active */
25 writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
32 #if defined(CONFIG_ARCH_CPU_INIT)
33 int arch_cpu_init(void)
36 * It might be necessary to flush data cache, if U-boot is loaded
37 * from kickstart bootloader, e.g. from S1L loader
44 #error "You have to select CONFIG_ARCH_CPU_INIT"
47 #if defined(CONFIG_DISPLAY_CPUINFO)
48 int print_cpuinfo(void)
50 printf("CPU: NXP LPC32XX\n");
51 printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
52 printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
53 printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);