1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
8 #include <asm/arch/cpu.h>
9 #include <asm/arch/clk.h>
10 #include <asm/arch/wdt.h>
11 #include <asm/arch/sys_proto.h>
14 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
15 static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
17 void reset_cpu(ulong addr)
19 /* Enable watchdog clock */
20 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
22 /* To be compatible with the original U-Boot code:
23 * addr: - 0: perform hard reset.
24 * - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
26 /* Reset pulse length is 13005 peripheral clock frames */
27 writel(13000, &wdt->pulse);
29 /* Force WDOG_RESET2 and RESOUT_N signal active */
30 writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
31 | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
33 /* Force match output active */
34 writel(0x01, &wdt->emr);
36 /* Internal reset on match output (no pulse on "RESOUT_N") */
37 writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
44 #if defined(CONFIG_ARCH_CPU_INIT)
45 int arch_cpu_init(void)
48 * It might be necessary to flush data cache, if U-Boot is loaded
49 * from kickstart bootloader, e.g. from S1L loader
56 #error "You have to select CONFIG_ARCH_CPU_INIT"
59 #if defined(CONFIG_DISPLAY_CPUINFO)
60 int print_cpuinfo(void)
62 printf("CPU: NXP LPC32XX\n");
63 printf("CPU clock: %uMHz\n", get_hclk_pll_rate() / 1000000);
64 printf("AHB bus clock: %uMHz\n", get_hclk_clk_rate() / 1000000);
65 printf("Peripheral clock: %uMHz\n", get_periph_clk_rate() / 1000000);
71 #ifdef CONFIG_LPC32XX_ETH
72 int cpu_eth_init(bd_t *bis)
74 lpc32xx_eth_initialize(bis);