4 * (C) Copyright 2014 DENX Software Engineering GmbH
5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
7 * This is called by SPL to gain access to the SDR DRAM.
9 * This code runs from SRAM.
11 * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided
12 * by the board configuration file.
14 * SPDX-License-Identifier: GPL-2.0+
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/clk.h>
21 #include <asm/arch/wdt.h>
22 #include <asm/arch/emc.h>
25 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
26 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
28 void ddr_init(struct emc_dram_settings *dram)
32 /* Enable EMC interface and choose little endian mode */
33 writel(1, &emc->ctrl);
34 writel(0, &emc->config);
35 /* Select maximum EMC Dynamic Memory Refresh Time */
36 writel(0x7FF, &emc->refresh);
38 ck = get_sdram_clk_rate();
40 writel(dram->cmddelay, &clk->sdramclk_ctrl);
41 writel(dram->config0, &emc->config0);
42 writel(dram->rascas0, &emc->rascas0);
43 writel(dram->rdconfig, &emc->read_config);
45 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp);
46 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras);
47 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex);
48 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr);
49 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc);
50 writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc);
51 writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr);
52 writel(dram->trrd, &emc->t_rrd);
53 writel(dram->tmrd, &emc->t_mrd);
54 writel(dram->tcdlr, &emc->t_cdlr);
56 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
58 /* Force all clocks, enable inverted ck, issue NOP command */
59 writel(0x00000193, &emc->control);
61 /* Keep all clocks enabled, issue a PRECHARGE ALL command */
62 writel(0x00000113, &emc->control);
63 /* Fast dynamic refresh for at least a few SDRAM ck cycles */
64 writel((((128) >> 4) & 0x7FF), &emc->refresh);
66 /* set correct dynamic refresh timing */
67 writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh);
69 /* set normal mode to CAS=3 */
70 writel(0x00000093, &emc->control);
71 readl(EMC_DYCS0_BASE | dram->mode);
72 /* set extended mode to all zeroes */
73 writel(0x00000093, &emc->control);
74 readl(EMC_DYCS0_BASE | dram->emode);
75 /* stop forcing clocks, keep inverted clock, issue normal mode */
76 writel(0x00000010, &emc->control);