1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2009 DENX Software Engineering
4 * Author: John Rigby <jrigby@gmail.com>
6 * Based on mx27/generic.c:
7 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
8 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
15 #include <asm/arch-imx/cpu.h>
16 #include <asm/arch/imx-regs.h>
17 #include <asm/arch/clock.h>
19 #ifdef CONFIG_FSL_ESDHC
20 #include <fsl_esdhc.h>
22 DECLARE_GLOBAL_DATA_PTR;
26 * get the system pll clock in Hz
28 * mfi + mfn / (mfd +1)
29 * f = 2 * f_ref * --------------------
32 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
34 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
36 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
38 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
40 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
43 mfi = mfi <= 5 ? 5 : mfi;
44 mfn = mfn >= 512 ? mfn - 1024 : mfn;
48 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
52 static ulong imx_get_mpllclk(void)
54 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
55 ulong fref = MXC_HCLK;
57 return imx_decode_pll(readl(&ccm->mpctl), fref);
60 static ulong imx_get_upllclk(void)
62 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
63 ulong fref = MXC_HCLK;
65 return imx_decode_pll(readl(&ccm->upctl), fref);
68 static ulong imx_get_armclk(void)
70 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
71 ulong cctl = readl(&ccm->cctl);
72 ulong fref = imx_get_mpllclk();
75 if (cctl & CCM_CCTL_ARM_SRC)
76 fref = lldiv((u64) fref * 3, 4);
78 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
79 & CCM_CCTL_ARM_DIV_MASK) + 1;
84 static ulong imx_get_ahbclk(void)
86 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
87 ulong cctl = readl(&ccm->cctl);
88 ulong fref = imx_get_armclk();
91 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
92 & CCM_CCTL_AHB_DIV_MASK) + 1;
97 static ulong imx_get_ipgclk(void)
99 return imx_get_ahbclk() / 2;
102 static ulong imx_get_perclk(int clk)
104 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
105 ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
109 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
110 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
115 int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
117 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
118 ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
119 ulong div = (fref + freq - 1) / freq;
121 if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
124 clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
125 CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
126 div << CCM_PERCLK_SHIFT(clk));
128 setbits_le32(&ccm->mcr, 1 << clk);
130 clrbits_le32(&ccm->mcr, 1 << clk);
134 unsigned int mxc_get_clock(enum mxc_clock clk)
136 if (clk >= MXC_CLK_NUM)
140 return imx_get_armclk();
142 return imx_get_ahbclk();
146 return imx_get_ipgclk();
148 return imx_get_perclk(clk);
152 u32 get_cpu_rev(void)
155 u32 system_rev = 0x25000;
157 /* read SREV register from IIM module */
158 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
159 srev = readl(&iim->iim_srev);
163 system_rev |= CHIP_REV_1_0;
166 system_rev |= CHIP_REV_1_1;
169 system_rev |= CHIP_REV_1_2;
172 system_rev |= 0x8000;
179 #if defined(CONFIG_DISPLAY_CPUINFO)
180 static char *get_reset_cause(void)
182 /* read RCSR register from CCM module */
183 struct ccm_regs *ccm =
184 (struct ccm_regs *)IMX_CCM_BASE;
186 u32 cause = readl(&ccm->rcsr) & 0x0f;
192 else if ((cause & 2) == 2)
194 else if ((cause & 4) == 4)
196 else if ((cause & 8) == 8)
199 return "unknown reset";
203 int print_cpuinfo(void)
206 u32 cpurev = get_cpu_rev();
208 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
209 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
210 ((cpurev & 0x8000) ? " unknown" : ""),
211 strmhz(buf, imx_get_armclk()));
212 printf("Reset cause: %s\n", get_reset_cause());
217 void enable_caches(void)
219 #ifndef CONFIG_SYS_DCACHE_OFF
220 /* Enable D-cache. I-cache is already enabled in start.S */
225 #if defined(CONFIG_FEC_MXC)
227 * Initializes on-chip ethernet controllers.
228 * to override, implement board_eth_init()
230 int cpu_eth_init(bd_t *bis)
232 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
235 val = readl(&ccm->cgr0);
237 writel(val, &ccm->cgr0);
238 return fecmxc_initialize(bis);
244 #ifdef CONFIG_FSL_ESDHC
245 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
246 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
248 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
254 #ifdef CONFIG_FSL_ESDHC
256 * Initializes on-chip MMC controllers.
257 * to override, implement board_mmc_init()
259 int cpu_mmc_init(bd_t *bis)
261 return fsl_esdhc_mmc_init(bis);
265 #ifdef CONFIG_FEC_MXC
266 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
269 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
270 struct fuse_bank *bank = &iim->bank[0];
271 struct fuse_bank0_regs *fuse =
272 (struct fuse_bank0_regs *)bank->fuse_regs;
274 for (i = 0; i < 6; i++)
275 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
277 #endif /* CONFIG_FEC_MXC */