2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on mx27/generic.c:
6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/imx25-pinmux.h>
31 #include <asm/arch/clock.h>
33 #ifdef CONFIG_FSL_ESDHC
34 #include <fsl_esdhc.h>
36 DECLARE_GLOBAL_DATA_PTR;
40 * get the system pll clock in Hz
42 * mfi + mfn / (mfd +1)
43 * f = 2 * f_ref * --------------------
46 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
48 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
50 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
52 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
54 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
57 mfi = mfi <= 5 ? 5 : mfi;
58 mfn = mfn >= 512 ? mfn - 1024 : mfn;
62 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
66 static ulong imx_get_mpllclk(void)
68 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
69 ulong fref = MXC_HCLK;
71 return imx_decode_pll(readl(&ccm->mpctl), fref);
74 static ulong imx_get_armclk(void)
76 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
77 ulong cctl = readl(&ccm->cctl);
78 ulong fref = imx_get_mpllclk();
81 if (cctl & CCM_CCTL_ARM_SRC)
82 fref = lldiv((u64) fref * 3, 4);
84 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
85 & CCM_CCTL_ARM_DIV_MASK) + 1;
90 static ulong imx_get_ahbclk(void)
92 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
93 ulong cctl = readl(&ccm->cctl);
94 ulong fref = imx_get_armclk();
97 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
98 & CCM_CCTL_AHB_DIV_MASK) + 1;
103 static ulong imx_get_ipgclk(void)
105 return imx_get_ahbclk() / 2;
108 static ulong imx_get_perclk(int clk)
110 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
111 ulong fref = imx_get_ahbclk();
114 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
115 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
120 unsigned int mxc_get_clock(enum mxc_clock clk)
122 if (clk >= MXC_CLK_NUM)
126 return imx_get_armclk();
128 return imx_get_ahbclk();
132 return imx_get_ipgclk();
134 return imx_get_perclk(clk);
138 u32 get_cpu_rev(void)
141 u32 system_rev = 0x25000;
143 /* read SREV register from IIM module */
144 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
145 srev = readl(&iim->iim_srev);
149 system_rev |= CHIP_REV_1_0;
152 system_rev |= CHIP_REV_1_1;
155 system_rev |= CHIP_REV_1_2;
158 system_rev |= 0x8000;
165 #if defined(CONFIG_DISPLAY_CPUINFO)
166 static char *get_reset_cause(void)
168 /* read RCSR register from CCM module */
169 struct ccm_regs *ccm =
170 (struct ccm_regs *)IMX_CCM_BASE;
172 u32 cause = readl(&ccm->rcsr) & 0x0f;
178 else if ((cause & 2) == 2)
180 else if ((cause & 4) == 4)
182 else if ((cause & 8) == 8)
185 return "unknown reset";
189 int print_cpuinfo(void)
192 u32 cpurev = get_cpu_rev();
194 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
195 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
196 ((cpurev & 0x8000) ? " unknown" : ""),
197 strmhz(buf, imx_get_armclk()));
198 printf("Reset cause: %s\n\n", get_reset_cause());
203 void enable_caches(void)
205 #ifndef CONFIG_SYS_DCACHE_OFF
206 /* Enable D-cache. I-cache is already enabled in start.S */
211 #if defined(CONFIG_FEC_MXC)
213 * Initializes on-chip ethernet controllers.
214 * to override, implement board_eth_init()
216 int cpu_eth_init(bd_t *bis)
218 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
221 val = readl(&ccm->cgr0);
223 writel(val, &ccm->cgr0);
224 return fecmxc_initialize(bis);
230 #ifdef CONFIG_FSL_ESDHC
231 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
232 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
234 gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
240 #ifdef CONFIG_FSL_ESDHC
242 * Initializes on-chip MMC controllers.
243 * to override, implement board_mmc_init()
245 int cpu_mmc_init(bd_t *bis)
247 return fsl_esdhc_mmc_init(bis);
251 #ifdef CONFIG_MXC_UART
252 void mx25_uart1_init_pins(void)
254 struct iomuxc_mux_ctl *muxctl;
255 struct iomuxc_pad_ctl *padctl;
260 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
261 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
262 muxmode0 = MX25_PIN_MUX_MODE(0);
264 * set up input pins with hysteresis and 100K pull-ups
266 inpadctl = MX25_PIN_PAD_CTL_HYS
267 | MX25_PIN_PAD_CTL_PKE
268 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PU;
271 * set up output pins with 100K pull-downs
272 * FIXME: need to revisit this
273 * PUE is ignored if PKE is not set
274 * so the right value here is likely
275 * 0x0 for no pull up/down
277 * 0xc0 for 100k pull down
279 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
283 writel(muxmode0, &muxctl->pad_uart1_rxd);
284 writel(inpadctl, &padctl->pad_uart1_rxd);
287 writel(muxmode0, &muxctl->pad_uart1_txd);
288 writel(outpadctl, &padctl->pad_uart1_txd);
291 writel(muxmode0, &muxctl->pad_uart1_rts);
292 writel(outpadctl, &padctl->pad_uart1_rts);
295 writel(muxmode0, &muxctl->pad_uart1_cts);
296 writel(inpadctl, &padctl->pad_uart1_cts);
298 #endif /* CONFIG_MXC_UART */
300 #ifdef CONFIG_FEC_MXC
301 void mx25_fec_init_pins(void)
303 struct iomuxc_mux_ctl *muxctl;
304 struct iomuxc_pad_ctl *padctl;
310 muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
311 padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
312 muxmode0 = MX25_PIN_MUX_MODE(0);
313 inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
314 | MX25_PIN_PAD_CTL_PKE
315 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
316 inpadctl_22kpu = MX25_PIN_PAD_CTL_HYS
317 | MX25_PIN_PAD_CTL_PKE
318 | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_22K_PU;
320 * set up output pins with 100K pull-downs
321 * FIXME: need to revisit this
322 * PUE is ignored if PKE is not set
323 * so the right value here is likely
326 * 0xc0 for 100k pull down
328 outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
331 writel(muxmode0, &muxctl->pad_fec_tx_clk);
332 writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
335 writel(muxmode0, &muxctl->pad_fec_rx_dv);
336 writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
339 writel(muxmode0, &muxctl->pad_fec_rdata0);
340 writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
343 writel(muxmode0, &muxctl->pad_fec_tdata0);
344 writel(outpadctl, &padctl->pad_fec_tdata0);
347 writel(muxmode0, &muxctl->pad_fec_tx_en);
348 writel(outpadctl, &padctl->pad_fec_tx_en);
351 writel(muxmode0, &muxctl->pad_fec_mdc);
352 writel(outpadctl, &padctl->pad_fec_mdc);
355 writel(muxmode0, &muxctl->pad_fec_mdio);
356 writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
359 writel(muxmode0, &muxctl->pad_fec_rdata1);
360 writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
363 writel(muxmode0, &muxctl->pad_fec_tdata1);
364 writel(outpadctl, &padctl->pad_fec_tdata1);
368 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
371 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
372 struct fuse_bank *bank = &iim->bank[0];
373 struct fuse_bank0_regs *fuse =
374 (struct fuse_bank0_regs *)bank->fuse_regs;
376 for (i = 0; i < 6; i++)
377 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
379 #endif /* CONFIG_FEC_MXC */