2 * (C) Copyright 2009 DENX Software Engineering
3 * Author: John Rigby <jrigby@gmail.com>
5 * Based on mx27/generic.c:
6 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
7 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/imx-regs.h>
30 #include <asm/arch/clock.h>
32 #ifdef CONFIG_FSL_ESDHC
33 #include <fsl_esdhc.h>
35 DECLARE_GLOBAL_DATA_PTR;
39 * get the system pll clock in Hz
41 * mfi + mfn / (mfd +1)
42 * f = 2 * f_ref * --------------------
45 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
47 unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
49 int mfn = (pll >> CCM_PLL_MFN_SHIFT)
51 unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
53 unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
56 mfi = mfi <= 5 ? 5 : mfi;
57 mfn = mfn >= 512 ? mfn - 1024 : mfn;
61 return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
65 static ulong imx_get_mpllclk(void)
67 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
68 ulong fref = MXC_HCLK;
70 return imx_decode_pll(readl(&ccm->mpctl), fref);
73 static ulong imx_get_armclk(void)
75 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
76 ulong cctl = readl(&ccm->cctl);
77 ulong fref = imx_get_mpllclk();
80 if (cctl & CCM_CCTL_ARM_SRC)
81 fref = lldiv((u64) fref * 3, 4);
83 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
84 & CCM_CCTL_ARM_DIV_MASK) + 1;
89 static ulong imx_get_ahbclk(void)
91 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
92 ulong cctl = readl(&ccm->cctl);
93 ulong fref = imx_get_armclk();
96 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
97 & CCM_CCTL_AHB_DIV_MASK) + 1;
102 static ulong imx_get_ipgclk(void)
104 return imx_get_ahbclk() / 2;
107 static ulong imx_get_perclk(int clk)
109 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
110 ulong fref = imx_get_ahbclk();
113 div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
114 div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
119 unsigned int mxc_get_clock(enum mxc_clock clk)
121 if (clk >= MXC_CLK_NUM)
125 return imx_get_armclk();
127 return imx_get_ahbclk();
131 return imx_get_ipgclk();
133 return imx_get_perclk(clk);
137 u32 get_cpu_rev(void)
140 u32 system_rev = 0x25000;
142 /* read SREV register from IIM module */
143 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
144 srev = readl(&iim->iim_srev);
148 system_rev |= CHIP_REV_1_0;
151 system_rev |= CHIP_REV_1_1;
154 system_rev |= CHIP_REV_1_2;
157 system_rev |= 0x8000;
164 #if defined(CONFIG_DISPLAY_CPUINFO)
165 static char *get_reset_cause(void)
167 /* read RCSR register from CCM module */
168 struct ccm_regs *ccm =
169 (struct ccm_regs *)IMX_CCM_BASE;
171 u32 cause = readl(&ccm->rcsr) & 0x0f;
177 else if ((cause & 2) == 2)
179 else if ((cause & 4) == 4)
181 else if ((cause & 8) == 8)
184 return "unknown reset";
188 int print_cpuinfo(void)
191 u32 cpurev = get_cpu_rev();
193 printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
194 (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
195 ((cpurev & 0x8000) ? " unknown" : ""),
196 strmhz(buf, imx_get_armclk()));
197 printf("Reset cause: %s\n\n", get_reset_cause());
202 void enable_caches(void)
204 #ifndef CONFIG_SYS_DCACHE_OFF
205 /* Enable D-cache. I-cache is already enabled in start.S */
210 #if defined(CONFIG_FEC_MXC)
212 * Initializes on-chip ethernet controllers.
213 * to override, implement board_eth_init()
215 int cpu_eth_init(bd_t *bis)
217 struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
220 val = readl(&ccm->cgr0);
222 writel(val, &ccm->cgr0);
223 return fecmxc_initialize(bis);
229 #ifdef CONFIG_FSL_ESDHC
230 #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
231 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
233 gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
239 #ifdef CONFIG_FSL_ESDHC
241 * Initializes on-chip MMC controllers.
242 * to override, implement board_mmc_init()
244 int cpu_mmc_init(bd_t *bis)
246 return fsl_esdhc_mmc_init(bis);
250 #ifdef CONFIG_FEC_MXC
251 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
254 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
255 struct fuse_bank *bank = &iim->bank[0];
256 struct fuse_bank0_regs *fuse =
257 (struct fuse_bank0_regs *)bank->fuse_regs;
259 for (i = 0; i < 6; i++)
260 mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
262 #endif /* CONFIG_FEC_MXC */