2 * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
3 * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/arch/imx-regs.h>
26 #include <asm/arch/clock.h>
27 #include <asm/arch/gpio.h>
29 #include <asm/arch/mxcmmc.h>
33 * get the system pll clock in Hz
35 * mfi + mfn / (mfd +1)
36 * f = 2 * f_ref * --------------------
39 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
41 unsigned int mfi = (pll >> 10) & 0xf;
42 unsigned int mfn = pll & 0x3ff;
43 unsigned int mfd = (pll >> 16) & 0x3ff;
44 unsigned int pd = (pll >> 26) & 0xf;
46 mfi = mfi <= 5 ? 5 : mfi;
48 return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
49 (mfd + 1) * (pd + 1));
52 static ulong clk_in_32k(void)
54 return 1024 * CONFIG_MX27_CLK32;
57 static ulong clk_in_26m(void)
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
61 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
63 return 26000000 * 2 / 3;
69 static ulong imx_get_mpllclk(void)
71 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
72 ulong cscr = readl(&pll->cscr);
75 if (cscr & CSCR_MCU_SEL)
80 return imx_decode_pll(readl(&pll->mpctl0), fref);
83 static ulong imx_get_armclk(void)
85 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
86 ulong cscr = readl(&pll->cscr);
87 ulong fref = imx_get_mpllclk();
90 if (!(cscr & CSCR_ARM_SRC_MPLL))
91 fref = lldiv((fref * 2), 3);
93 div = ((cscr >> 12) & 0x3) + 1;
95 return lldiv(fref, div);
98 static ulong imx_get_ahbclk(void)
100 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
101 ulong cscr = readl(&pll->cscr);
102 ulong fref = imx_get_mpllclk();
105 div = ((cscr >> 8) & 0x3) + 1;
107 return lldiv(fref * 2, 3 * div);
110 static __attribute__((unused)) ulong imx_get_spllclk(void)
112 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
113 ulong cscr = readl(&pll->cscr);
116 if (cscr & CSCR_SP_SEL)
121 return imx_decode_pll(readl(&pll->spctl0), fref);
124 static ulong imx_decode_perclk(ulong div)
126 return lldiv((imx_get_mpllclk() * 2), (div * 3));
129 static ulong imx_get_perclk1(void)
131 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
133 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
136 static ulong imx_get_perclk2(void)
138 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
140 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
143 static __attribute__((unused)) ulong imx_get_perclk3(void)
145 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
147 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
150 static __attribute__((unused)) ulong imx_get_perclk4(void)
152 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
154 return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
157 unsigned int mxc_get_clock(enum mxc_clock clk)
161 return imx_get_armclk();
163 return imx_get_perclk1();
165 return imx_get_ahbclk();
167 return imx_get_perclk2();
173 #if defined(CONFIG_DISPLAY_CPUINFO)
174 int print_cpuinfo (void)
178 printf("CPU: Freescale i.MX27 at %s MHz\n\n",
179 strmhz(buf, imx_get_mpllclk()));
184 int cpu_eth_init(bd_t *bis)
186 #if defined(CONFIG_FEC_MXC)
187 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
189 /* enable FEC clock */
190 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
191 writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
192 return fecmxc_initialize(bis);
199 * Initializes on-chip MMC controllers.
200 * to override, implement board_mmc_init()
202 int cpu_mmc_init(bd_t *bis)
204 #ifdef CONFIG_MXC_MMC
205 return mxc_mmc_init(bis);
211 void imx_gpio_mode(int gpio_mode)
213 struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
214 unsigned int pin = gpio_mode & GPIO_PIN_MASK;
215 unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
216 unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
217 unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
218 unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
222 if (gpio_mode & GPIO_PUEN) {
223 writel(readl(®s->port[port].puen) | (1 << pin),
224 ®s->port[port].puen);
226 writel(readl(®s->port[port].puen) & ~(1 << pin),
227 ®s->port[port].puen);
231 if (gpio_mode & GPIO_OUT) {
232 writel(readl(®s->port[port].gpio_dir) | 1 << pin,
233 ®s->port[port].gpio_dir);
235 writel(readl(®s->port[port].gpio_dir) & ~(1 << pin),
236 ®s->port[port].gpio_dir);
239 /* Primary / alternate function */
240 if (gpio_mode & GPIO_AF) {
241 writel(readl(®s->port[port].gpr) | (1 << pin),
242 ®s->port[port].gpr);
244 writel(readl(®s->port[port].gpr) & ~(1 << pin),
245 ®s->port[port].gpr);
249 if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
250 writel(readl(®s->port[port].gius) | (1 << pin),
251 ®s->port[port].gius);
253 writel(readl(®s->port[port].gius) & ~(1 << pin),
254 ®s->port[port].gius);
257 /* Output / input configuration */
259 tmp = readl(®s->port[port].ocr1);
260 tmp &= ~(3 << (pin * 2));
261 tmp |= (ocr << (pin * 2));
262 writel(tmp, ®s->port[port].ocr1);
264 writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)),
265 ®s->port[port].iconfa1);
266 writel(readl(®s->port[port].iconfa1) | aout << (pin * 2),
267 ®s->port[port].iconfa1);
268 writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)),
269 ®s->port[port].iconfb1);
270 writel(readl(®s->port[port].iconfb1) | bout << (pin * 2),
271 ®s->port[port].iconfb1);
275 tmp = readl(®s->port[port].ocr2);
276 tmp &= ~(3 << (pin * 2));
277 tmp |= (ocr << (pin * 2));
278 writel(tmp, ®s->port[port].ocr2);
280 writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)),
281 ®s->port[port].iconfa2);
282 writel(readl(®s->port[port].iconfa2) | aout << (pin * 2),
283 ®s->port[port].iconfa2);
284 writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)),
285 ®s->port[port].iconfb2);
286 writel(readl(®s->port[port].iconfb2) | bout << (pin * 2),
287 ®s->port[port].iconfb2);
291 #ifdef CONFIG_MXC_UART
292 void mx27_uart1_init_pins(void)
295 unsigned int mode[] = {
300 for (i = 0; i < ARRAY_SIZE(mode); i++)
301 imx_gpio_mode(mode[i]);
304 #endif /* CONFIG_MXC_UART */
306 #ifdef CONFIG_FEC_MXC
307 void mx27_fec_init_pins(void)
310 unsigned int mode[] = {
320 PD9_AIN_FEC_MDC | GPIO_PUEN,
322 PD11_AOUT_FEC_TX_CLK,
331 for (i = 0; i < ARRAY_SIZE(mode); i++)
332 imx_gpio_mode(mode[i]);
335 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
338 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
339 struct fuse_bank *bank = &iim->bank[0];
340 struct fuse_bank0_regs *fuse =
341 (struct fuse_bank0_regs *)bank->fuse_regs;
343 for (i = 0; i < 6; i++)
344 mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
346 #endif /* CONFIG_FEC_MXC */
348 #ifdef CONFIG_MXC_MMC
349 void mx27_sd1_init_pins(void)
352 unsigned int mode[] = {
361 for (i = 0; i < ARRAY_SIZE(mode); i++)
362 imx_gpio_mode(mode[i]);
366 void mx27_sd2_init_pins(void)
369 unsigned int mode[] = {
378 for (i = 0; i < ARRAY_SIZE(mode); i++)
379 imx_gpio_mode(mode[i]);
382 #endif /* CONFIG_MXC_MMC */