2 * Freescale i.MX23/i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/imx-common/dma.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/iomux.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
38 #include <linux/compiler.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
43 inline void lowlevel_init(void) {}
45 void reset_cpu(ulong ignored) __attribute__((noreturn));
47 void reset_cpu(ulong ignored)
49 struct mxs_rtc_regs *rtc_regs =
50 (struct mxs_rtc_regs *)MXS_RTC_BASE;
51 struct mxs_lcdif_regs *lcdif_regs =
52 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
55 * Shut down the LCD controller as it interferes with BootROM boot mode
58 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
60 /* Wait 1 uS before doing the actual watchdog reset */
61 writel(1, &rtc_regs->hw_rtc_watchdog);
62 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
64 /* Endless loop, reset will exit from here */
69 void enable_caches(void)
71 #ifndef CONFIG_SYS_ICACHE_OFF
74 #ifndef CONFIG_SYS_DCACHE_OFF
80 * This function will craft a jumptable at 0x0 which will redirect interrupt
81 * vectoring to proper location of U-Boot in RAM.
83 * The structure of the jumptable will be as follows:
84 * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
85 * <destination address> ... for each previous ldr, thus also repeated 8 times
87 * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
88 * offset 0x18 from current value of PC register. Note that PC is already
89 * incremented by 4 when computing the offset, so the effective offset is
90 * actually 0x20, this the associated <destination address>. Loading the PC
91 * register with an address performs a jump to that address.
93 void mx28_fixup_vt(uint32_t start_addr)
95 /* ldr pc, [pc, #0x18] */
96 const uint32_t ldr_pc = 0xe59ff018;
97 /* Jumptable location is 0x0 */
98 uint32_t *vt = (uint32_t *)0x0;
101 for (i = 0; i < 8; i++) {
103 vt[i + 8] = start_addr + (4 * i);
107 #ifdef CONFIG_ARCH_MISC_INIT
108 int arch_misc_init(void)
110 mx28_fixup_vt(gd->relocaddr);
115 int arch_cpu_init(void)
117 struct mxs_clkctrl_regs *clkctrl_regs =
118 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
119 extern uint32_t _start;
121 mx28_fixup_vt((uint32_t)&_start);
126 /* Clear bypass bit */
127 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
128 &clkctrl_regs->hw_clkctrl_clkseq_set);
130 /* Set GPMI clock to ref_gpmi / 12 */
131 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
132 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
137 * Configure GPIO unit
141 #ifdef CONFIG_APBH_DMA
149 #if defined(CONFIG_DISPLAY_CPUINFO)
150 static const char *get_cpu_type(void)
152 struct mxs_digctl_regs *digctl_regs =
153 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
155 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
156 case HW_DIGCTL_CHIPID_MX23:
158 case HW_DIGCTL_CHIPID_MX28:
165 static const char *get_cpu_rev(void)
167 struct mxs_digctl_regs *digctl_regs =
168 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
169 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
171 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
172 case HW_DIGCTL_CHIPID_MX23:
187 case HW_DIGCTL_CHIPID_MX28:
199 int print_cpuinfo(void)
201 struct mxs_spl_data *data = (struct mxs_spl_data *)
202 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
204 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
207 mxc_get_clock(MXC_ARM_CLK) / 1000000);
208 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
213 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
215 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
216 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
217 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
218 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
223 * Initializes on-chip ethernet controllers.
225 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
226 int cpu_eth_init(bd_t *bis)
228 struct mxs_clkctrl_regs *clkctrl_regs =
229 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
231 /* Turn on ENET clocks */
232 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
233 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
235 /* Set up ENET PLL for 50 MHz */
236 /* Power on ENET PLL */
237 writel(CLKCTRL_PLL2CTRL0_POWER,
238 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
242 /* Gate on ENET PLL */
243 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
244 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
246 /* Enable pad output */
247 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
253 __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
256 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
258 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
262 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
264 #define MXS_OCOTP_MAX_TIMEOUT 1000000
265 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
267 struct mxs_ocotp_regs *ocotp_regs =
268 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
273 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
275 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
276 MXS_OCOTP_MAX_TIMEOUT)) {
277 printf("MXS FEC: Can't get MAC from OCOTP\n");
281 data = readl(&ocotp_regs->hw_ocotp_cust0);
283 mac[2] = (data >> 24) & 0xff;
284 mac[3] = (data >> 16) & 0xff;
285 mac[4] = (data >> 8) & 0xff;
286 mac[5] = data & 0xff;
287 mx28_adjust_mac(dev_id, mac);
290 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
296 int mxs_dram_init(void)
298 struct mxs_spl_data *data = (struct mxs_spl_data *)
299 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
301 if (data->mem_dram_size == 0) {
303 "Error, the RAM size passed up from SPL is 0!\n");
307 gd->ram_size = data->mem_dram_size;
312 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,