2 * Freescale i.MX23/i.MX28 common code
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/errno.h>
32 #include <asm/arch/clock.h>
33 #include <asm/imx-common/dma.h>
34 #include <asm/arch/gpio.h>
35 #include <asm/arch/iomux.h>
36 #include <asm/arch/imx-regs.h>
37 #include <asm/arch/sys_proto.h>
38 #include <linux/compiler.h>
40 DECLARE_GLOBAL_DATA_PTR;
42 /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
43 inline void lowlevel_init(void) {}
45 void reset_cpu(ulong ignored) __attribute__((noreturn));
47 void reset_cpu(ulong ignored)
49 struct mxs_rtc_regs *rtc_regs =
50 (struct mxs_rtc_regs *)MXS_RTC_BASE;
51 struct mxs_lcdif_regs *lcdif_regs =
52 (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
55 * Shut down the LCD controller as it interferes with BootROM boot mode
58 writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
60 /* Wait 1 uS before doing the actual watchdog reset */
61 writel(1, &rtc_regs->hw_rtc_watchdog);
62 writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
64 /* Endless loop, reset will exit from here */
69 void enable_caches(void)
71 #ifndef CONFIG_SYS_ICACHE_OFF
74 #ifndef CONFIG_SYS_DCACHE_OFF
79 void mx28_fixup_vt(uint32_t start_addr)
81 uint32_t *vt = (uint32_t *)0x20;
84 for (i = 0; i < 8; i++)
85 vt[i] = start_addr + (4 * i);
88 #ifdef CONFIG_ARCH_MISC_INIT
89 int arch_misc_init(void)
91 mx28_fixup_vt(gd->relocaddr);
96 int arch_cpu_init(void)
98 struct mxs_clkctrl_regs *clkctrl_regs =
99 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
100 extern uint32_t _start;
102 mx28_fixup_vt((uint32_t)&_start);
107 /* Clear bypass bit */
108 writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
109 &clkctrl_regs->hw_clkctrl_clkseq_set);
111 /* Set GPMI clock to ref_gpmi / 12 */
112 clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
113 CLKCTRL_GPMI_CLKGATE | CLKCTRL_GPMI_DIV_MASK, 1);
118 * Configure GPIO unit
122 #ifdef CONFIG_APBH_DMA
130 #if defined(CONFIG_DISPLAY_CPUINFO)
131 static const char *get_cpu_type(void)
133 struct mxs_digctl_regs *digctl_regs =
134 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
136 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
137 case HW_DIGCTL_CHIPID_MX23:
139 case HW_DIGCTL_CHIPID_MX28:
146 static const char *get_cpu_rev(void)
148 struct mxs_digctl_regs *digctl_regs =
149 (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
150 uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
152 switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
153 case HW_DIGCTL_CHIPID_MX23:
168 case HW_DIGCTL_CHIPID_MX28:
180 int print_cpuinfo(void)
182 struct mxs_spl_data *data = (struct mxs_spl_data *)
183 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
185 printf("CPU: Freescale i.MX%s rev%s at %d MHz\n",
188 mxc_get_clock(MXC_ARM_CLK) / 1000000);
189 printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
194 int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
196 printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
197 printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
198 printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
199 printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
204 * Initializes on-chip ethernet controllers.
206 #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
207 int cpu_eth_init(bd_t *bis)
209 struct mxs_clkctrl_regs *clkctrl_regs =
210 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
212 /* Turn on ENET clocks */
213 clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
214 CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
216 /* Set up ENET PLL for 50 MHz */
217 /* Power on ENET PLL */
218 writel(CLKCTRL_PLL2CTRL0_POWER,
219 &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
223 /* Gate on ENET PLL */
224 writel(CLKCTRL_PLL2CTRL0_CLKGATE,
225 &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
227 /* Enable pad output */
228 setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
234 __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
237 mac[1] = 0x04; /* Use FSL vendor MAC address by default */
239 if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
243 #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
245 #define MXS_OCOTP_MAX_TIMEOUT 1000000
246 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
248 struct mxs_ocotp_regs *ocotp_regs =
249 (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
254 writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
256 if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
257 MXS_OCOTP_MAX_TIMEOUT)) {
258 printf("MXS FEC: Can't get MAC from OCOTP\n");
262 data = readl(&ocotp_regs->hw_ocotp_cust0);
264 mac[2] = (data >> 24) & 0xff;
265 mac[3] = (data >> 16) & 0xff;
266 mac[4] = (data >> 8) & 0xff;
267 mac[5] = data & 0xff;
268 mx28_adjust_mac(dev_id, mac);
271 void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
277 int mxs_dram_init(void)
279 struct mxs_spl_data *data = (struct mxs_spl_data *)
280 ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
282 if (data->mem_dram_size == 0) {
284 "Error, the RAM size passed up from SPL is 0!\n");
288 gd->ram_size = data->mem_dram_size;
293 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,