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   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Freescale i.MX28 Battery measurement init
   4  *
   5  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   6  * on behalf of DENX Software Engineering GmbH
   7  */
   8
   9 #include <common.h>
  10 #include <config.h>
  11 #include <asm/io.h>
  12 #include <asm/arch/imx-regs.h>
  13
  14 #include "mxs_init.h"
  15
  16 void mxs_lradc_init(void)
  17 {
  18         struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  19
  20         debug("SPL: Initialisating LRADC\n");
  21
  22         writel(LRADC_CTRL0_SFTRST, &regs->hw_lradc_ctrl0_clr);
  23         writel(LRADC_CTRL0_CLKGATE, &regs->hw_lradc_ctrl0_clr);
  24         writel(LRADC_CTRL0_ONCHIP_GROUNDREF, &regs->hw_lradc_ctrl0_clr);
  25
  26         clrsetbits_le32(&regs->hw_lradc_ctrl3,
  27                         LRADC_CTRL3_CYCLE_TIME_MASK,
  28                         LRADC_CTRL3_CYCLE_TIME_6MHZ);
  29
  30         clrsetbits_le32(&regs->hw_lradc_ctrl4,
  31                         LRADC_CTRL4_LRADC7SELECT_MASK |
  32                         LRADC_CTRL4_LRADC6SELECT_MASK,
  33                         LRADC_CTRL4_LRADC7SELECT_CHANNEL7 |
  34                         LRADC_CTRL4_LRADC6SELECT_CHANNEL10);
  35 }
  36
  37 void mxs_lradc_enable_batt_measurement(void)
  38 {
  39         struct mxs_lradc_regs *regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE;
  40
  41         debug("SPL: Enabling LRADC battery measurement\n");
  42
  43         /* Check if the channel is present at all. */
  44         if (!(readl(&regs->hw_lradc_status) & LRADC_STATUS_CHANNEL7_PRESENT)) {
  45                 debug("SPL: LRADC channel 7 is not present - aborting\n");
  46                 return;
  47         }
  48
  49         debug("SPL: LRADC channel 7 is present - configuring\n");
  50
  51         writel(LRADC_CTRL1_LRADC7_IRQ_EN, &regs->hw_lradc_ctrl1_clr);
  52         writel(LRADC_CTRL1_LRADC7_IRQ, &regs->hw_lradc_ctrl1_clr);
  53
  54         clrsetbits_le32(&regs->hw_lradc_conversion,
  55                         LRADC_CONVERSION_SCALE_FACTOR_MASK,
  56                         LRADC_CONVERSION_SCALE_FACTOR_LI_ION);
  57         writel(LRADC_CONVERSION_AUTOMATIC, &regs->hw_lradc_conversion_set);
  58
  59         /* Configure the channel. */
  60         writel((1 << 7) << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
  61                 &regs->hw_lradc_ctrl2_clr);
  62         writel(0xffffffff, &regs->hw_lradc_ch7_clr);
  63         clrbits_le32(&regs->hw_lradc_ch7, LRADC_CH_NUM_SAMPLES_MASK);
  64         writel(LRADC_CH_ACCUMULATE, &regs->hw_lradc_ch7_clr);
  65
  66         /* Schedule the channel. */
  67         writel(1 << 7, &regs->hw_lradc_ctrl0_set);
  68
  69         /* Start the channel sampling. */
  70         writel(((1 << 7) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) |
  71                 ((1 << 3) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) |
  72                 100, &regs->hw_lradc_delay3);
  73
  74         writel(0xffffffff, &regs->hw_lradc_ch7_clr);
  75         writel(LRADC_DELAY_KICK, &regs->hw_lradc_delay3_set);
  76
  77         debug("SPL: LRADC channel 7 configuration complete\n");
  78 }