2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Groger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Zupke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * Change to support call back into iMX28 bootrom
16 * Copyright (c) 2011 Marek Vasut <marek.vasut@gmail.com>
17 * on behalf of DENX Software Engineering GmbH
19 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm-offsets.h>
28 *************************************************************************
30 * Jump vector table as in table 3.1 in [1]
32 *************************************************************************
39 b undefined_instruction
48 * Vector table, located at address 0x20.
49 * This table allows the code running AFTER SPL, the U-Boot, to install it's
50 * interrupt handlers here. The problem is that the U-Boot is loaded into RAM,
51 * including it's interrupt vectoring table and the table at 0x0 is still the
52 * SPLs. So if interrupt happens in U-Boot, the SPLs interrupt vectoring table
57 _vt_undefined_instruction:
59 _vt_software_interrupt:
74 undefined_instruction:
75 ldr pc, _vt_undefined_instruction
77 ldr pc, _vt_software_interrupt
79 ldr pc, _vt_prefetch_abort
81 ldr pc, _vt_data_abort
89 .balignl 16,0xdeadbeef
92 *************************************************************************
94 * Startup Code (reset vector)
96 * do important init only if we don't start from memory!
97 * setup Memory and board specific bits prior to relocation.
98 * relocate armboot to ram
101 *************************************************************************
106 #ifdef CONFIG_SPL_TEXT_BASE
107 .word CONFIG_SPL_TEXT_BASE
109 .word CONFIG_SYS_TEXT_BASE
113 * These are defined in the board-specific linker script.
114 * Subtracting _start from them lets the linker put their
115 * relative position in the executable instead of leaving
118 .globl _bss_start_ofs
120 .word __bss_start - _start
124 .word __bss_end - _start
130 #ifdef CONFIG_USE_IRQ
131 /* IRQ stack memory (calculated at run-time) */
132 .globl IRQ_STACK_START
136 /* IRQ stack memory (calculated at run-time) */
137 .globl FIQ_STACK_START
142 /* IRQ stack memory (calculated at run-time) + 8 bytes */
143 .globl IRQ_STACK_START_IN
148 * the actual reset code
153 * If the CPU is configured in "Wait JTAG connection mode", the stack
154 * pointer is not configured and is zero. This will cause crash when
155 * trying to push data onto stack right below here. Load the SP and make
156 * it point to the end of OCRAM if the SP is zero.
159 ldreq sp, =CONFIG_SYS_INIT_SP_ADDR
162 * Store all registers on old stack pointer, this will allow us later to
163 * return to the BootROM and let the BootROM load U-Boot into RAM.
165 * WARNING: Register r0 and r1 are used by the BootROM to pass data
166 * to the called code. Register r0 will contain arbitrary
167 * data that are set in the BootStream. In case this code
168 * was started with CALL instruction, register r1 will contain
169 * pointer to the return value this function can then set.
170 * The code below MUST NOT CHANGE register r0 and r1 !
174 /* Save control register c1 */
175 mrc p15, 0, r2, c1, c0, 0
178 /* Set the cpu to SVC32 mode and store old CPSR register content. */
187 /* Restore BootROM's CPU mode (especially FIQ). */
192 * Restore c1 register. Especially set exception vector location
193 * back to BootROM space which is required by bootrom for USB boot.
196 mcr p15, 0, r2, c1, c0, 0
201 * In case this code was started by the CALL instruction, the register
202 * r0 is examined by the BootROM after this code returns. The value in
203 * r0 must be set to 0 to indicate successful return.
210 ldr sp, _TEXT_BASE /* switch to abort stack */
212 bl 1b /* hang and never return */