3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/pantheon.h>
13 #define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
14 #define SET_MRVL_ID (1<<8)
15 #define L2C_RAM_SEL (1<<4)
17 int arch_cpu_init(void)
20 struct panthcpu_registers *cpuregs =
21 (struct panthcpu_registers*) PANTHEON_CPU_BASE;
23 struct panthapb_registers *apbclkres =
24 (struct panthapb_registers*) PANTHEON_APBC_BASE;
26 struct panthmpmu_registers *mpmu =
27 (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
29 struct panthapmu_registers *apmu =
30 (struct panthapmu_registers *) PANTHEON_APMU_BASE;
32 /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
33 val = readl(&cpuregs->cpu_conf);
34 val = val | SET_MRVL_ID;
35 writel(val, &cpuregs->cpu_conf);
37 /* Turn on clock gating (PMUM_CCGR) */
38 writel(0xFFFFFFFF, &mpmu->ccgr);
40 /* Turn on clock gating (PMUM_ACGR) */
41 writel(0xFFFFFFFF, &mpmu->acgr);
43 /* Turn on uart2 clock */
44 writel(UARTCLK14745KHZ, &apbclkres->uart0);
46 /* Enable GPIO clock */
47 writel(APBC_APBCLK, &apbclkres->gpio);
50 /* Enable I2C clock */
51 writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
52 writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
55 #ifdef CONFIG_MV_SDHCI
56 /* Enable mmc clock */
57 writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
59 writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
68 #if defined(CONFIG_DISPLAY_CPUINFO)
69 int print_cpuinfo(void)
72 struct panthcpu_registers *cpuregs =
73 (struct panthcpu_registers*) PANTHEON_CPU_BASE;
75 id = readl(&cpuregs->chip_id);
76 printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
82 void i2c_clk_enable(void)