3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
26 #include <asm/arch/pantheon.h>
30 * Refer 6.2.9 in Datasheet
32 struct panthtmr_registers {
33 u32 clk_ctrl; /* Timer clk control reg */
34 u32 match[9]; /* Timer match registers */
35 u32 count[3]; /* Timer count registers */
38 u32 preload[3]; /* Timer preload value */
46 u32 cer; /* Timer count enable reg */
55 #define TIMER 0 /* Use TIMER 0 */
56 /* Each timer has 3 match registers */
57 #define MATCH_CMP(x) ((3 * TIMER) + x)
58 #define TIMER_LOAD_VAL 0xffffffff
59 #define COUNT_RD_REQ 0x1
61 DECLARE_GLOBAL_DATA_PTR;
62 /* Using gd->tbu from timestamp and gd->tbl for lastdec */
65 * For preventing risk of instability in reading counter value,
66 * first set read request to register cvwr and then read same
67 * register after it captures counter value.
69 ulong read_timer(void)
71 struct panthtmr_registers *panthtimers =
72 (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
73 volatile int loop=100;
76 writel(COUNT_RD_REQ, &panthtimers->cvwr);
78 val = readl(&panthtimers->cvwr);
81 * This stop gcc complain and prevent loop mistake init to 0
83 val = readl(&panthtimers->cvwr);
88 ulong get_timer_masked(void)
90 ulong now = read_timer();
94 gd->tbu += now - gd->tbl;
96 /* we have an overflow ... */
97 gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
104 ulong get_timer(ulong base)
106 return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
110 void __udelay(unsigned long usec)
115 delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
116 endtime = get_timer_masked() + delayticks;
118 while (get_timer_masked() < endtime)
127 struct panthapb_registers *apb1clkres =
128 (struct panthapb_registers *) PANTHEON_APBC_BASE;
129 struct panthtmr_registers *panthtimers =
130 (struct panthtmr_registers *) PANTHEON_TIMER_BASE;
132 /* Enable Timer clock at 3.25 MHZ */
133 writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
135 /* load value into timer */
136 writel(0x0, &panthtimers->clk_ctrl);
137 /* Use Timer 0 Match Resiger 0 */
138 writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]);
139 /* Preload value is 0 */
140 writel(0x0, &panthtimers->preload[TIMER]);
141 /* Enable match comparator 0 for Timer 0 */
142 writel(0x1, &panthtimers->preload_ctrl[TIMER]);
145 writel(0x1, &panthtimers->cer);
146 /* init the gd->tbu and gd->tbl value */
147 gd->tbl = read_timer();
153 #define MPMU_APRR_WDTR (1<<4)
154 #define TMR_WFAR 0xbaba /* WDT Register First key */
155 #define TMP_WSAR 0xeb10 /* WDT Register Second key */
158 * This function uses internal Watchdog Timer
159 * based reset mechanism.
160 * Steps to write watchdog registers (protected access)
161 * 1. Write key value to TMR_WFAR reg.
162 * 2. Write key value to TMP_WSAR reg.
163 * 3. Perform write operation.
165 void reset_cpu (unsigned long ignored)
167 struct panthmpmu_registers *mpmu =
168 (struct panthmpmu_registers *) PANTHEON_MPMU_BASE;
169 struct panthtmr_registers *panthtimers =
170 (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE;
173 /* negate hardware reset to the WDT after system reset */
174 val = readl(&mpmu->aprr);
175 val = val | MPMU_APRR_WDTR;
176 writel(val, &mpmu->aprr);
178 /* reset/enable WDT clock */
179 writel(APBC_APBCLK, &mpmu->wdtpcr);
181 /* clear previous WDT status */
182 writel(TMR_WFAR, &panthtimers->wfar);
183 writel(TMP_WSAR, &panthtimers->wsar);
184 writel(0, &panthtimers->wdt_sts);
186 /* set match counter */
187 writel(TMR_WFAR, &panthtimers->wfar);
188 writel(TMP_WSAR, &panthtimers->wsar);
189 writel(0xf, &panthtimers->wdt_match_r);
191 /* enable WDT reset */
192 writel(TMR_WFAR, &panthtimers->wfar);
193 writel(TMP_WSAR, &panthtimers->wsar);
194 writel(0x3, &panthtimers->wdt_match_en);
196 /*enable functional WDT clock */
197 writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);