2 * (C) Copyright 2000-2009
3 * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
4 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/hardware.h>
12 #include <asm/arch/spr_misc.h>
13 #include <asm/arch/spr_defs.h>
15 static void sel_1v8(void)
17 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
20 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
23 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
25 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
28 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
30 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
34 static void sel_2v5(void)
36 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
39 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
42 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
44 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
47 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
49 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
56 void plat_ddr_init(void)
58 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
60 u32 core3v3, ddr1v8, ddr2v5;
62 /* DDR pad register configurations */
63 ddrpad = readl(&misc_p->ddr_pad);
64 ddrpad &= ~DDR_PAD_CNF_MSK;
68 #elif (CONFIG_DDR_2HCLK)
70 #elif (CONFIG_DDR_PLL2)
73 writel(ddrpad, &misc_p->ddr_pad);
75 /* Compensation register configurations */
76 core3v3 = readl(&misc_p->core_3v3_compensation);
77 core3v3 &= 0x8080ffe0;
78 core3v3 |= 0x78000002;
79 writel(core3v3, &misc_p->core_3v3_compensation);
81 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
84 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
86 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
89 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
91 if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
92 /* Software memory configuration */
93 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
98 /* Hardware memory configuration */
99 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
111 /* Nothing to be done for SPEAr600 */
117 * return true if the particular booting option is selected
118 * return false otherwise
120 static u32 read_bootstrap(void)
122 return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
123 & CONFIG_SPEAR_BOOTSTRAPMASK;
126 int snor_boot_selected(void)
128 u32 bootstrap = read_bootstrap();
130 if (SNOR_BOOT_SUPPORTED) {
131 /* Check whether SNOR boot is selected */
132 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
133 CONFIG_SPEAR_ONLYSNORBOOT)
136 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
137 CONFIG_SPEAR_NORNAND8BOOT)
140 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
141 CONFIG_SPEAR_NORNAND16BOOT)
148 int nand_boot_selected(void)
150 u32 bootstrap = read_bootstrap();
152 if (NAND_BOOT_SUPPORTED) {
153 /* Check whether NAND boot is selected */
154 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
155 CONFIG_SPEAR_NORNAND8BOOT)
158 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
159 CONFIG_SPEAR_NORNAND16BOOT)
166 int pnor_boot_selected(void)
168 /* Parallel NOR boot is not selected in any SPEAr600 revision */
172 int usb_boot_selected(void)
174 u32 bootstrap = read_bootstrap();
176 if (USB_BOOT_SUPPORTED) {
177 /* Check whether USB boot is selected */
178 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
185 int tftp_boot_selected(void)
187 /* TFTP boot is not selected in any SPEAr600 revision */
191 int uart_boot_selected(void)
193 /* UART boot is not selected in any SPEAr600 revision */
197 int spi_boot_selected(void)
199 /* SPI boot is not selected in any SPEAr600 revision */
203 int i2c_boot_selected(void)
205 /* I2C boot is not selected in any SPEAr600 revision */
209 int mmc_boot_selected(void)
214 void plat_late_init(void)