2 * (C) Copyright 2000-2009
3 * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
4 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/hardware.h>
28 #include <asm/arch/spr_misc.h>
29 #include <asm/arch/spr_defs.h>
31 static void sel_1v8(void)
33 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
36 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
39 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
41 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
44 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
46 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
50 static void sel_2v5(void)
52 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
55 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
58 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
60 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
63 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
65 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
72 void plat_ddr_init(void)
74 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
76 u32 core3v3, ddr1v8, ddr2v5;
78 /* DDR pad register configurations */
79 ddrpad = readl(&misc_p->ddr_pad);
80 ddrpad &= ~DDR_PAD_CNF_MSK;
84 #elif (CONFIG_DDR_2HCLK)
86 #elif (CONFIG_DDR_PLL2)
89 writel(ddrpad, &misc_p->ddr_pad);
91 /* Compensation register configurations */
92 core3v3 = readl(&misc_p->core_3v3_compensation);
93 core3v3 &= 0x8080ffe0;
94 core3v3 |= 0x78000002;
95 writel(core3v3, &misc_p->core_3v3_compensation);
97 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
100 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
102 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
103 ddr2v5 &= 0x8080ffc0;
104 ddr2v5 |= 0x78000004;
105 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
107 if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
108 /* Software memory configuration */
109 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
114 /* Hardware memory configuration */
115 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
127 /* Nothing to be done for SPEAr600 */
133 * return true if the particular booting option is selected
134 * return false otherwise
136 static u32 read_bootstrap(void)
138 return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
139 & CONFIG_SPEAR_BOOTSTRAPMASK;
142 int snor_boot_selected(void)
144 u32 bootstrap = read_bootstrap();
146 if (SNOR_BOOT_SUPPORTED) {
147 /* Check whether SNOR boot is selected */
148 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
149 CONFIG_SPEAR_ONLYSNORBOOT)
152 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
153 CONFIG_SPEAR_NORNAND8BOOT)
156 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
157 CONFIG_SPEAR_NORNAND16BOOT)
164 int nand_boot_selected(void)
166 u32 bootstrap = read_bootstrap();
168 if (NAND_BOOT_SUPPORTED) {
169 /* Check whether NAND boot is selected */
170 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
171 CONFIG_SPEAR_NORNAND8BOOT)
174 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
175 CONFIG_SPEAR_NORNAND16BOOT)
182 int pnor_boot_selected(void)
184 /* Parallel NOR boot is not selected in any SPEAr600 revision */
188 int usb_boot_selected(void)
190 u32 bootstrap = read_bootstrap();
192 if (USB_BOOT_SUPPORTED) {
193 /* Check whether USB boot is selected */
194 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
201 int tftp_boot_selected(void)
203 /* TFTP boot is not selected in any SPEAr600 revision */
207 int uart_boot_selected(void)
209 /* UART boot is not selected in any SPEAr600 revision */
213 int spi_boot_selected(void)
215 /* SPI boot is not selected in any SPEAr600 revision */
219 int i2c_boot_selected(void)
221 /* I2C boot is not selected in any SPEAr600 revision */
225 int mmc_boot_selected(void)
230 void plat_late_init(void)