2 * (C) Copyright 2000-2009
3 * Viresh Kumar, ST Microelectronics, viresh.kumar@st.com
4 * Vipin Kumar, ST Microelectronics, vipin.kumar@st.com
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/hardware.h>
28 #include <asm/arch/spr_misc.h>
29 #include <asm/arch/spr_defs.h>
34 static void sel_1v8(void)
36 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
39 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
42 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
44 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
47 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
49 while (!(readl(&misc_p->ddr_1v8_compensation) & DDR_COMP_ACCURATE))
53 static void sel_2v5(void)
55 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
58 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
61 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
63 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
66 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
68 while (!(readl(&misc_p->ddr_2v5_compensation) & DDR_COMP_ACCURATE))
75 void plat_ddr_init(void)
77 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
79 u32 core3v3, ddr1v8, ddr2v5;
81 /* DDR pad register configurations */
82 ddrpad = readl(&misc_p->ddr_pad);
83 ddrpad &= ~DDR_PAD_CNF_MSK;
87 #elif (CONFIG_DDR_2HCLK)
89 #elif (CONFIG_DDR_PLL2)
92 writel(ddrpad, &misc_p->ddr_pad);
94 /* Compensation register configurations */
95 core3v3 = readl(&misc_p->core_3v3_compensation);
96 core3v3 &= 0x8080ffe0;
97 core3v3 |= 0x78000002;
98 writel(core3v3, &misc_p->core_3v3_compensation);
100 ddr1v8 = readl(&misc_p->ddr_1v8_compensation);
101 ddr1v8 &= 0x8080ffc0;
102 ddr1v8 |= 0x78000004;
103 writel(ddr1v8, &misc_p->ddr_1v8_compensation);
105 ddr2v5 = readl(&misc_p->ddr_2v5_compensation);
106 ddr2v5 &= 0x8080ffc0;
107 ddr2v5 |= 0x78000004;
108 writel(ddr2v5, &misc_p->ddr_2v5_compensation);
110 if ((readl(&misc_p->ddr_pad) & DDR_PAD_SW_CONF) == DDR_PAD_SW_CONF) {
111 /* Software memory configuration */
112 if (readl(&misc_p->ddr_pad) & DDR_PAD_SSTL_SEL)
117 /* Hardware memory configuration */
118 if (readl(&misc_p->ddr_pad) & DDR_PAD_DRAM_TYPE)
130 /* Nothing to be done for SPEAr600 */
136 * return TRUE if the particular booting option is selected
137 * return FALSE otherwise
139 static u32 read_bootstrap(void)
141 return (readl(CONFIG_SPEAR_BOOTSTRAPCFG) >> CONFIG_SPEAR_BOOTSTRAPSHFT)
142 & CONFIG_SPEAR_BOOTSTRAPMASK;
145 int snor_boot_selected(void)
147 u32 bootstrap = read_bootstrap();
149 if (SNOR_BOOT_SUPPORTED) {
150 /* Check whether SNOR boot is selected */
151 if ((bootstrap & CONFIG_SPEAR_ONLYSNORBOOT) ==
152 CONFIG_SPEAR_ONLYSNORBOOT)
155 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
156 CONFIG_SPEAR_NORNAND8BOOT)
159 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
160 CONFIG_SPEAR_NORNAND16BOOT)
167 int nand_boot_selected(void)
169 u32 bootstrap = read_bootstrap();
171 if (NAND_BOOT_SUPPORTED) {
172 /* Check whether NAND boot is selected */
173 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
174 CONFIG_SPEAR_NORNAND8BOOT)
177 if ((bootstrap & CONFIG_SPEAR_NORNANDBOOT) ==
178 CONFIG_SPEAR_NORNAND16BOOT)
185 int pnor_boot_selected(void)
187 /* Parallel NOR boot is not selected in any SPEAr600 revision */
191 int usb_boot_selected(void)
193 u32 bootstrap = read_bootstrap();
195 if (USB_BOOT_SUPPORTED) {
196 /* Check whether USB boot is selected */
197 if (!(bootstrap & CONFIG_SPEAR_USBBOOT))
204 int tftp_boot_selected(void)
206 /* TFTP boot is not selected in any SPEAr600 revision */
210 int uart_boot_selected(void)
212 /* UART boot is not selected in any SPEAr600 revision */
216 int spi_boot_selected(void)
218 /* SPI boot is not selected in any SPEAr600 revision */
222 int i2c_boot_selected(void)
224 /* I2C boot is not selected in any SPEAr600 revision */
228 int mmc_boot_selected(void)
233 void plat_late_init(void)