3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/spr_defs.h>
15 #include <asm/arch/spr_misc.h>
16 #include <asm/arch/spr_syscntl.h>
18 static void ddr_clock_init(void)
20 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
23 clkenb = readl(&misc_p->periph1_clken);
24 clkenb &= ~PERIPH_MPMCMSK;
25 clkenb |= PERIPH_MPMC_WE;
27 /* Intentionally done twice */
28 writel(clkenb, &misc_p->periph1_clken);
29 writel(clkenb, &misc_p->periph1_clken);
31 ddrpll = readl(&misc_p->pll_ctr_reg);
32 ddrpll &= ~MEM_CLK_SEL_MSK;
34 ddrpll |= MEM_CLK_HCLK;
35 #elif (CONFIG_DDR_2HCLK)
36 ddrpll |= MEM_CLK_2HCLK;
37 #elif (CONFIG_DDR_PLL2)
38 ddrpll |= MEM_CLK_PLL2;
40 #error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
42 writel(ddrpll, &misc_p->pll_ctr_reg);
44 writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
45 &misc_p->periph1_clken);
48 static void mpmc_init_values(void)
51 u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
52 u32 *mpmc_val_p = &mpmc_conf_vals[0];
54 for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
55 writel(*mpmc_val_p, mpmc_reg_p);
57 mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
60 * MPMC controller start
61 * MPMC waiting for DLLLOCKREG high
63 writel(0x01000100, &mpmc_reg_p[7]);
65 while (!(readl(&mpmc_reg_p[3]) & 0x10000))
69 static void mpmc_init(void)
71 /* Clock related settings for DDR */
75 * DDR pad register bits are different for different SoCs
76 * Compensation values are also handled separately
80 /* Initialize mpmc register values */
84 static void pll_init(void)
86 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
89 writel(FREQ_332, &misc_p->pll1_frq);
90 writel(0x1C0A, &misc_p->pll1_cntl);
91 writel(0x1C0E, &misc_p->pll1_cntl);
92 writel(0x1C06, &misc_p->pll1_cntl);
93 writel(0x1C0E, &misc_p->pll1_cntl);
95 writel(FREQ_332, &misc_p->pll2_frq);
96 writel(0x1C0A, &misc_p->pll2_cntl);
97 writel(0x1C0E, &misc_p->pll2_cntl);
98 writel(0x1C06, &misc_p->pll2_cntl);
99 writel(0x1C0E, &misc_p->pll2_cntl);
101 /* wait for pll locks */
102 while (!(readl(&misc_p->pll1_cntl) & 0x1))
104 while (!(readl(&misc_p->pll2_cntl) & 0x1))
108 static void mac_init(void)
110 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
112 writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
113 &misc_p->periph1_clken);
115 writel(SYNTH23, &misc_p->gmac_synth_clk);
117 switch (get_socrev()) {
118 case SOC_SPEAR600_AA:
119 case SOC_SPEAR600_AB:
120 case SOC_SPEAR600_BA:
121 case SOC_SPEAR600_BB:
122 case SOC_SPEAR600_BC:
123 case SOC_SPEAR600_BD:
124 writel(0x0, &misc_p->gmac_ctr_reg);
130 writel(0x4, &misc_p->gmac_ctr_reg);
134 writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
135 &misc_p->periph1_clken);
137 writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
138 &misc_p->periph1_rst);
139 writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
140 &misc_p->periph1_rst);
143 static void sys_init(void)
145 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
146 struct syscntl_regs *syscntl_p =
147 (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
149 /* Set system state to SLOW */
150 writel(SLOW, &syscntl_p->scctrl);
151 writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
153 /* Initialize PLLs */
157 * Ethernet configuration
158 * To be done only if the tftp boot is not selected already
159 * Boot code ensures the correct configuration in tftp booting
161 if (!tftp_boot_selected())
164 writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
165 writel(0x555, &misc_p->amba_clk_cfg);
167 writel(NORMAL, &syscntl_p->scctrl);
169 /* Wait for system to switch to normal mode */
170 while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
179 * @return SOC_SPEARXXX
183 #if defined(CONFIG_SPEAR600)
184 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
185 u32 soc_id = readl(&misc_p->soc_core_id);
186 u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
187 u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
189 if ((pri_socid == 'B') && (sec_socid == 'B'))
190 return SOC_SPEAR600_BB;
191 else if ((pri_socid == 'B') && (sec_socid == 'C'))
192 return SOC_SPEAR600_BC;
193 else if ((pri_socid == 'B') && (sec_socid == 'D'))
194 return SOC_SPEAR600_BD;
195 else if (soc_id == 0)
196 return SOC_SPEAR600_BA;
199 #elif defined(CONFIG_SPEAR300)
201 #elif defined(CONFIG_SPEAR310)
203 #elif defined(CONFIG_SPEAR320)
208 void lowlevel_init(void)
210 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
211 const char *u_boot_rev = U_BOOT_VERSION;
213 /* Initialize PLLs */
216 /* Initialize UART */
219 /* Print U-Boot SPL version string */
220 serial_puts("\nU-Boot SPL ");
221 /* Avoid a second "U-Boot" coming from this string */
222 u_boot_rev = &u_boot_rev[7];
223 serial_puts(u_boot_rev);
225 serial_puts(U_BOOT_DATE);
227 serial_puts(U_BOOT_TIME);
230 #if defined(CONFIG_OS_BOOT)
231 writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
232 &misc_p->periph1_clken);
235 /* Enable IPs (release reset) */
236 writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
238 /* Initialize MPMC */
239 serial_puts("Configure DDR\n");
242 /* SoC specific initialization */
246 void spear_late_init(void)
248 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
250 writel(0x80000007, &misc_p->arb_icm_ml1);
251 writel(0x80000007, &misc_p->arb_icm_ml2);
252 writel(0x80000007, &misc_p->arb_icm_ml3);
253 writel(0x80000007, &misc_p->arb_icm_ml4);
254 writel(0x80000007, &misc_p->arb_icm_ml5);
255 writel(0x80000007, &misc_p->arb_icm_ml6);
256 writel(0x80000007, &misc_p->arb_icm_ml7);
257 writel(0x80000007, &misc_p->arb_icm_ml8);
258 writel(0x80000007, &misc_p->arb_icm_ml9);