3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/arch/hardware.h>
30 #include <asm/arch/spr_defs.h>
31 #include <asm/arch/spr_misc.h>
32 #include <asm/arch/spr_syscntl.h>
34 inline void hang(void)
36 serial_puts("### ERROR ### Please RESET the board ###\n");
41 static void ddr_clock_init(void)
43 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
46 clkenb = readl(&misc_p->periph1_clken);
47 clkenb &= ~PERIPH_MPMCMSK;
48 clkenb |= PERIPH_MPMC_WE;
50 /* Intentionally done twice */
51 writel(clkenb, &misc_p->periph1_clken);
52 writel(clkenb, &misc_p->periph1_clken);
54 ddrpll = readl(&misc_p->pll_ctr_reg);
55 ddrpll &= ~MEM_CLK_SEL_MSK;
57 ddrpll |= MEM_CLK_HCLK;
58 #elif (CONFIG_DDR_2HCLK)
59 ddrpll |= MEM_CLK_2HCLK;
60 #elif (CONFIG_DDR_PLL2)
61 ddrpll |= MEM_CLK_PLL2;
63 #error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
65 writel(ddrpll, &misc_p->pll_ctr_reg);
67 writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
68 &misc_p->periph1_clken);
71 static void mpmc_init_values(void)
74 u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
75 u32 *mpmc_val_p = &mpmc_conf_vals[0];
77 for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
78 writel(*mpmc_val_p, mpmc_reg_p);
80 mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
83 * MPMC controller start
84 * MPMC waiting for DLLLOCKREG high
86 writel(0x01000100, &mpmc_reg_p[7]);
88 while (!(readl(&mpmc_reg_p[3]) & 0x10000))
92 static void mpmc_init(void)
94 /* Clock related settings for DDR */
98 * DDR pad register bits are different for different SoCs
99 * Compensation values are also handled separately
103 /* Initialize mpmc register values */
107 static void pll_init(void)
109 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
111 /* Initialize PLLs */
112 writel(FREQ_332, &misc_p->pll1_frq);
113 writel(0x1C0A, &misc_p->pll1_cntl);
114 writel(0x1C0E, &misc_p->pll1_cntl);
115 writel(0x1C06, &misc_p->pll1_cntl);
116 writel(0x1C0E, &misc_p->pll1_cntl);
118 writel(FREQ_332, &misc_p->pll2_frq);
119 writel(0x1C0A, &misc_p->pll2_cntl);
120 writel(0x1C0E, &misc_p->pll2_cntl);
121 writel(0x1C06, &misc_p->pll2_cntl);
122 writel(0x1C0E, &misc_p->pll2_cntl);
124 /* wait for pll locks */
125 while (!(readl(&misc_p->pll1_cntl) & 0x1))
127 while (!(readl(&misc_p->pll2_cntl) & 0x1))
131 static void mac_init(void)
133 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
135 writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
136 &misc_p->periph1_clken);
138 writel(SYNTH23, &misc_p->gmac_synth_clk);
140 switch (get_socrev()) {
141 case SOC_SPEAR600_AA:
142 case SOC_SPEAR600_AB:
143 case SOC_SPEAR600_BA:
144 case SOC_SPEAR600_BB:
145 case SOC_SPEAR600_BC:
146 case SOC_SPEAR600_BD:
147 writel(0x0, &misc_p->gmac_ctr_reg);
153 writel(0x4, &misc_p->gmac_ctr_reg);
157 writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
158 &misc_p->periph1_clken);
160 writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
161 &misc_p->periph1_rst);
162 writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
163 &misc_p->periph1_rst);
166 static void sys_init(void)
168 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
169 struct syscntl_regs *syscntl_p =
170 (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
172 /* Set system state to SLOW */
173 writel(SLOW, &syscntl_p->scctrl);
174 writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
176 /* Initialize PLLs */
180 * Ethernet configuration
181 * To be done only if the tftp boot is not selected already
182 * Boot code ensures the correct configuration in tftp booting
184 if (!tftp_boot_selected())
187 writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
188 writel(0x555, &misc_p->amba_clk_cfg);
190 writel(NORMAL, &syscntl_p->scctrl);
192 /* Wait for system to switch to normal mode */
193 while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
202 * @return SOC_SPEARXXX
206 #if defined(CONFIG_SPEAR600)
207 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
208 u32 soc_id = readl(&misc_p->soc_core_id);
209 u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
210 u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
212 if ((pri_socid == 'B') && (sec_socid == 'B'))
213 return SOC_SPEAR600_BB;
214 else if ((pri_socid == 'B') && (sec_socid == 'C'))
215 return SOC_SPEAR600_BC;
216 else if ((pri_socid == 'B') && (sec_socid == 'D'))
217 return SOC_SPEAR600_BD;
218 else if (soc_id == 0)
219 return SOC_SPEAR600_BA;
222 #elif defined(CONFIG_SPEAR300)
224 #elif defined(CONFIG_SPEAR310)
226 #elif defined(CONFIG_SPEAR320)
231 void lowlevel_init(void)
233 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
234 const char *u_boot_rev = U_BOOT_VERSION;
236 /* Initialize PLLs */
239 /* Initialize UART */
242 /* Print U-Boot SPL version string */
243 serial_puts("\nU-Boot SPL ");
244 /* Avoid a second "U-Boot" coming from this string */
245 u_boot_rev = &u_boot_rev[7];
246 serial_puts(u_boot_rev);
248 serial_puts(U_BOOT_DATE);
250 serial_puts(U_BOOT_TIME);
253 #if defined(CONFIG_OS_BOOT)
254 writel(readl(&misc_p->periph1_clken) | PERIPH_UART1,
255 &misc_p->periph1_clken);
258 /* Enable IPs (release reset) */
259 writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
261 /* Initialize MPMC */
262 serial_puts("Configure DDR\n");
265 /* SoC specific initialization */
269 void spear_late_init(void)
271 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
273 writel(0x80000007, &misc_p->arb_icm_ml1);
274 writel(0x80000007, &misc_p->arb_icm_ml2);
275 writel(0x80000007, &misc_p->arb_icm_ml3);
276 writel(0x80000007, &misc_p->arb_icm_ml4);
277 writel(0x80000007, &misc_p->arb_icm_ml5);
278 writel(0x80000007, &misc_p->arb_icm_ml6);
279 writel(0x80000007, &misc_p->arb_icm_ml7);
280 writel(0x80000007, &misc_p->arb_icm_ml8);
281 writel(0x80000007, &misc_p->arb_icm_ml9);