2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * SPDX-License-Identifier: GPL-2.0+
23 ldr pc, _undefined_instruction
24 ldr pc, _software_interrupt
25 ldr pc, _prefetch_abort
31 _undefined_instruction:
44 *************************************************************************
46 * Startup Code (reset vector)
48 * Below are the critical initializations already taken place in BootROM.
49 * So, these are not taken care in Xloader
50 * 1. Relocation to RAM
51 * 2. Initializing stacks
53 *************************************************************************
57 * the actual reset code
62 * Xloader has to return back to BootROM in a few cases.
63 * eg. Ethernet boot, UART boot, USB boot
64 * Saving registers for returning back
66 stmdb sp!, {r0-r12,r14}
69 * Clearing bss area is not done in Xloader.
70 * BSS area lies in the DDR location which is not yet initialized
71 * bss is assumed to be uninitialized.
74 ldmia sp!, {r0-r12,pc}
77 *************************************************************************
79 * CPU_init_critical registers
81 * setup important registers
84 *************************************************************************
91 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
92 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
95 * enable instruction cache
97 mrc p15, 0, r0, c1, c0, 0
98 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
99 mcr p15, 0, r0, c1, c0, 0
102 * Go setup Memory and board specific bits prior to relocation.
105 bl lowlevel_init /* go setup pll,mux,memory */