2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
39 ldr pc, _undefined_instruction
40 ldr pc, _software_interrupt
41 ldr pc, _prefetch_abort
47 _undefined_instruction:
60 *************************************************************************
62 * Startup Code (reset vector)
64 * Below are the critical initializations already taken place in BootROM.
65 * So, these are not taken care in Xloader
66 * 1. Relocation to RAM
67 * 2. Initializing stacks
69 *************************************************************************
73 * the actual reset code
78 * Xloader has to return back to BootROM in a few cases.
79 * eg. Ethernet boot, UART boot, USB boot
80 * Saving registers for returning back
82 stmdb sp!, {r0-r12,r14}
85 * Clearing bss area is not done in Xloader.
86 * BSS area lies in the DDR location which is not yet initialized
87 * bss is assumed to be uninitialized.
90 ldmia sp!, {r0-r12,pc}
93 *************************************************************************
95 * CPU_init_critical registers
97 * setup important registers
100 *************************************************************************
104 * flush v4 I/D caches
107 mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
108 mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
111 * enable instruction cache
113 mrc p15, 0, r0, c1, c0, 0
114 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
115 mcr p15, 0, r0, c1, c0, 0
118 * Go setup Memory and board specific bits prior to relocation.
121 bl lowlevel_init /* go setup pll,mux,memory */