2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm-offsets.h>
39 #if defined(CONFIG_OMAP1610)
40 #include <./configs/omap1510.h>
41 #elif defined(CONFIG_OMAP730)
42 #include <./configs/omap730.h>
46 *************************************************************************
48 * Jump vector table as in table 3.1 in [1]
50 *************************************************************************
54 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
59 .word CONFIG_SYS_DV_NOR_BOOT_CFG
66 #ifdef CONFIG_SPL_BUILD
67 /* No exception handlers in preloader */
78 /* pad to 64 byte boundary */
87 ldr pc, _undefined_instruction
88 ldr pc, _software_interrupt
89 ldr pc, _prefetch_abort
95 _undefined_instruction:
96 .word undefined_instruction
98 .word software_interrupt
110 #endif /* CONFIG_SPL_BUILD */
111 .balignl 16,0xdeadbeef
115 *************************************************************************
117 * Startup Code (reset vector)
119 * do important init only if we don't start from memory!
120 * setup Memory and board specific bits prior to relocation.
121 * relocate armboot to ram
124 *************************************************************************
129 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
130 .word CONFIG_SYS_TEXT_BASE
132 #ifdef CONFIG_SPL_BUILD
133 .word CONFIG_SPL_TEXT_BASE
135 .word CONFIG_SYS_TEXT_BASE
140 * These are defined in the board-specific linker script.
141 * Subtracting _start from them lets the linker put their
142 * relative position in the executable instead of leaving
145 .globl _bss_start_ofs
147 .word __bss_start - _start
151 .word __bss_end__ - _start
157 #ifdef CONFIG_NAND_U_BOOT
163 #ifdef CONFIG_USE_IRQ
164 /* IRQ stack memory (calculated at run-time) */
165 .globl IRQ_STACK_START
169 /* IRQ stack memory (calculated at run-time) */
170 .globl FIQ_STACK_START
175 /* IRQ stack memory (calculated at run-time) + 8 bytes */
176 .globl IRQ_STACK_START_IN
181 * the actual reset code
186 * set the cpu to SVC32 mode
194 * we do sys-critical inits only at reboot,
195 * not when booting from ram!
197 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
201 /* Set stackpointer in internal RAM to call board_init_f */
203 #ifdef CONFIG_NAND_SPL /* deprecated, use instead CONFIG_SPL_BUILD */
204 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
206 #ifdef CONFIG_SPL_BUILD
207 ldr sp, =(CONFIG_SPL_STACK)
209 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
212 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
216 /*------------------------------------------------------------------------------*/
218 #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_NAND_SPL)
220 * void relocate_code (addr_sp, gd, addr_moni)
222 * This "function" does not return, instead it continues in RAM
223 * after relocating the monitor code.
228 mov r4, r0 /* save addr_sp */
229 mov r5, r1 /* save addr of gd */
230 mov r6, r2 /* save addr of destination */
232 /* Set up the stack */
237 sub r9, r6, r0 /* r9 <- relocation offset */
239 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
240 beq clear_bss /* skip relocation */
241 mov r1, r6 /* r1 <- scratch for copy loop */
242 ldr r3, _bss_start_ofs
243 add r2, r0, r3 /* r2 <- source end address */
246 ldmia r0!, {r9-r10} /* copy from source address [r0] */
247 stmia r1!, {r9-r10} /* copy to target address [r1] */
248 cmp r0, r2 /* until source end address [r2] */
251 #ifndef CONFIG_SPL_BUILD
253 * fix .rel.dyn relocations
255 ldr r0, _TEXT_BASE /* r0 <- Text base */
256 sub r9, r6, r0 /* r9 <- relocation offset */
257 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
258 add r10, r10, r0 /* r10 <- sym table in FLASH */
259 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
260 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
261 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
262 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
264 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
265 add r0, r0, r9 /* r0 <- location to fix up in RAM */
268 cmp r7, #23 /* relative fixup? */
270 cmp r7, #2 /* absolute fixup? */
272 /* ignore unknown type of fixup */
275 /* absolute fix: set location to (offset) symbol value */
276 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
277 add r1, r10, r1 /* r1 <- address of symbol in table */
278 ldr r1, [r1, #4] /* r1 <- symbol value */
279 add r1, r1, r9 /* r1 <- relocated sym addr */
282 /* relative fix: increase location by offset */
287 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
293 #ifdef CONFIG_SPL_BUILD
294 /* No relocation for SPL */
298 ldr r0, _bss_start_ofs
300 mov r4, r6 /* reloc addr */
304 mov r2, #0x00000000 /* clear */
306 clbss_l:cmp r0, r1 /* clear loop... */
307 bhs clbss_e /* if reached end of bss, exit */
313 #ifndef CONFIG_SPL_BUILD
319 * We are done. Do not return, instead branch to second part of board
320 * initialization, now running from RAM.
322 #ifdef CONFIG_NAND_SPL
323 ldr r0, _nand_boot_ofs
329 ldr r0, _board_init_r_ofs
333 /* setup parameters for board_init_r */
334 mov r0, r5 /* gd_t */
335 mov r1, r6 /* dest_addr */
340 .word board_init_r - _start
344 .word __rel_dyn_start - _start
346 .word __rel_dyn_end - _start
348 .word __dynsym_start - _start
352 *************************************************************************
354 * CPU_init_critical registers
356 * setup important registers
357 * setup memory timing
359 *************************************************************************
361 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
364 * flush D cache before disabling it
368 mrc p15, 0, r15, c7, c10, 3
371 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
372 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
375 * disable MMU and D cache
376 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
378 mrc p15, 0, r0, c1, c0, 0
379 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
380 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
381 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
382 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
384 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
386 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
387 #ifndef CONFIG_SYS_ICACHE_OFF
388 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
390 mcr p15, 0, r0, c1, c0, 0
393 * Go setup Memory and board specific bits prior to relocation.
395 mov ip, lr /* perserve link reg across call */
396 bl lowlevel_init /* go setup pll,mux,memory */
397 mov lr, ip /* restore link */
398 mov pc, lr /* back to my caller */
399 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
401 #ifndef CONFIG_SPL_BUILD
403 *************************************************************************
407 *************************************************************************
413 #define S_FRAME_SIZE 72
435 #define MODE_SVC 0x13
439 * use bad_save_user_regs for abort/prefetch/undef/swi ...
440 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
443 .macro bad_save_user_regs
444 @ carve out a frame on current user stack
445 sub sp, sp, #S_FRAME_SIZE
446 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
447 ldr r2, IRQ_STACK_START_IN
448 @ get values for "aborted" pc and cpsr (into parm regs)
450 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
453 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
454 mov r0, sp @ save current stack into r0 (param register)
457 .macro irq_save_user_regs
458 sub sp, sp, #S_FRAME_SIZE
459 stmia sp, {r0 - r12} @ Calling r0-r12
460 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
462 stmdb r8, {sp, lr}^ @ Calling SP, LR
463 str lr, [r8, #0] @ Save calling PC
465 str r6, [r8, #4] @ Save CPSR
466 str r0, [r8, #8] @ Save OLD_R0
470 .macro irq_restore_user_regs
471 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
473 ldr lr, [sp, #S_PC] @ Get PC
474 add sp, sp, #S_FRAME_SIZE
475 subs pc, lr, #4 @ return & move spsr_svc into cpsr
479 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
481 str lr, [r13] @ save caller lr in position 0 of saved stack
482 mrs lr, spsr @ get the spsr
483 str lr, [r13, #4] @ save spsr in position 1 of saved stack
484 mov r13, #MODE_SVC @ prepare SVC-Mode
486 msr spsr, r13 @ switch modes, make sure moves will execute
487 mov lr, pc @ capture return pc
488 movs pc, lr @ jump to next instruction & switch modes.
491 .macro get_irq_stack @ setup IRQ stack
492 ldr sp, IRQ_STACK_START
495 .macro get_fiq_stack @ setup FIQ stack
496 ldr sp, FIQ_STACK_START
498 #endif /* CONFIG_SPL_BUILD */
503 #ifdef CONFIG_SPL_BUILD
506 ldr sp, _TEXT_BASE /* switch to abort stack */
508 bl 1b /* hang and never return */
509 #else /* !CONFIG_SPL_BUILD */
511 undefined_instruction:
514 bl do_undefined_instruction
520 bl do_software_interrupt
540 #ifdef CONFIG_USE_IRQ
547 irq_restore_user_regs
552 /* someone ought to write a more effiction fiq_save_user_regs */
555 irq_restore_user_regs
572 #endif /* CONFIG_SPL_BUILD */