2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
13 * Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
15 * See file CREDITS for list of people who contributed to this
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm-offsets.h>
40 *************************************************************************
42 * Jump vector table as in table 3.1 in [1]
44 *************************************************************************
48 #ifdef CONFIG_SYS_DV_NOR_BOOT_CFG
53 .word CONFIG_SYS_DV_NOR_BOOT_CFG
60 #ifdef CONFIG_SPL_BUILD
61 /* No exception handlers in preloader */
72 /* pad to 64 byte boundary */
81 ldr pc, _undefined_instruction
82 ldr pc, _software_interrupt
83 ldr pc, _prefetch_abort
89 _undefined_instruction:
90 .word undefined_instruction
92 .word software_interrupt
104 #endif /* CONFIG_SPL_BUILD */
105 .balignl 16,0xdeadbeef
109 *************************************************************************
111 * Startup Code (reset vector)
113 * do important init only if we don't start from memory!
114 * setup Memory and board specific bits prior to relocation.
115 * relocate armboot to ram
118 *************************************************************************
123 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE)
124 .word CONFIG_SPL_TEXT_BASE
126 .word CONFIG_SYS_TEXT_BASE
130 * These are defined in the board-specific linker script.
131 * Subtracting _start from them lets the linker put their
132 * relative position in the executable instead of leaving
135 .globl _bss_start_ofs
137 .word __bss_start - _start
141 .word __bss_end - _start
147 #ifdef CONFIG_USE_IRQ
148 /* IRQ stack memory (calculated at run-time) */
149 .globl IRQ_STACK_START
153 /* IRQ stack memory (calculated at run-time) */
154 .globl FIQ_STACK_START
159 /* IRQ stack memory (calculated at run-time) + 8 bytes */
160 .globl IRQ_STACK_START_IN
165 * the actual reset code
170 * set the cpu to SVC32 mode
178 * we do sys-critical inits only at reboot,
179 * not when booting from ram!
181 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
187 /*------------------------------------------------------------------------------*/
189 .globl c_runtime_cpu_setup
195 *************************************************************************
197 * CPU_init_critical registers
199 * setup important registers
200 * setup memory timing
202 *************************************************************************
204 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
207 * flush D cache before disabling it
211 mrc p15, 0, r15, c7, c10, 3
214 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
215 mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
218 * disable MMU and D cache
219 * enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
221 mrc p15, 0, r0, c1, c0, 0
222 bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
223 bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
224 #ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
225 orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
227 bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
229 orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
230 #ifndef CONFIG_SYS_ICACHE_OFF
231 orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
233 mcr p15, 0, r0, c1, c0, 0
236 * Go setup Memory and board specific bits prior to relocation.
238 mov ip, lr /* perserve link reg across call */
239 bl lowlevel_init /* go setup pll,mux,memory */
240 mov lr, ip /* restore link */
241 mov pc, lr /* back to my caller */
242 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
244 #ifndef CONFIG_SPL_BUILD
246 *************************************************************************
250 *************************************************************************
256 #define S_FRAME_SIZE 72
278 #define MODE_SVC 0x13
282 * use bad_save_user_regs for abort/prefetch/undef/swi ...
283 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
286 .macro bad_save_user_regs
287 @ carve out a frame on current user stack
288 sub sp, sp, #S_FRAME_SIZE
289 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
290 ldr r2, IRQ_STACK_START_IN
291 @ get values for "aborted" pc and cpsr (into parm regs)
293 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
296 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
297 mov r0, sp @ save current stack into r0 (param register)
300 .macro irq_save_user_regs
301 sub sp, sp, #S_FRAME_SIZE
302 stmia sp, {r0 - r12} @ Calling r0-r12
303 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
305 stmdb r8, {sp, lr}^ @ Calling SP, LR
306 str lr, [r8, #0] @ Save calling PC
308 str r6, [r8, #4] @ Save CPSR
309 str r0, [r8, #8] @ Save OLD_R0
313 .macro irq_restore_user_regs
314 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
316 ldr lr, [sp, #S_PC] @ Get PC
317 add sp, sp, #S_FRAME_SIZE
318 subs pc, lr, #4 @ return & move spsr_svc into cpsr
322 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
324 str lr, [r13] @ save caller lr in position 0 of saved stack
325 mrs lr, spsr @ get the spsr
326 str lr, [r13, #4] @ save spsr in position 1 of saved stack
327 mov r13, #MODE_SVC @ prepare SVC-Mode
329 msr spsr, r13 @ switch modes, make sure moves will execute
330 mov lr, pc @ capture return pc
331 movs pc, lr @ jump to next instruction & switch modes.
334 .macro get_irq_stack @ setup IRQ stack
335 ldr sp, IRQ_STACK_START
338 .macro get_fiq_stack @ setup FIQ stack
339 ldr sp, FIQ_STACK_START
341 #endif /* CONFIG_SPL_BUILD */
346 #ifdef CONFIG_SPL_BUILD
349 ldr sp, _TEXT_BASE /* switch to abort stack */
351 bl 1b /* hang and never return */
352 #else /* !CONFIG_SPL_BUILD */
354 undefined_instruction:
357 bl do_undefined_instruction
363 bl do_software_interrupt
383 #ifdef CONFIG_USE_IRQ
390 irq_restore_user_regs
395 /* someone ought to write a more effiction fiq_save_user_regs */
398 irq_restore_user_regs
415 #endif /* CONFIG_SPL_BUILD */