2 * armboot - Startup Code for ARM926EJS CPU-core
4 * Copyright (c) 2003 Texas Instruments
6 * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
8 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
9 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
10 * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
11 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
12 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
14 * See file CREDITS for list of people who contributed to this
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm-offsets.h>
38 *************************************************************************
42 *************************************************************************
48 ldr pc, _undefined_instruction
49 ldr pc, _software_interrupt
50 ldr pc, _prefetch_abort
56 _undefined_instruction:
57 .word undefined_instruction
59 .word software_interrupt
71 .balignl 16,0xdeadbeef
74 *************************************************************************
76 * Startup Code (reset vector)
78 * do important init only if we don't start from memory!
79 * setup memory and board specific bits prior to relocation.
80 * relocate armboot to ram
83 *************************************************************************
88 .word CONFIG_SYS_TEXT_BASE /* address of _start in the linked image */
91 * These are defined in the board-specific linker script.
92 * Subtracting _start from them lets the linker put their
93 * relative position in the executable instead of leaving
98 .word __bss_start - _start
102 .word __bss_end__ - _start
108 #ifdef CONFIG_USE_IRQ
109 /* IRQ stack memory (calculated at run-time) */
110 .globl IRQ_STACK_START
114 /* IRQ stack memory (calculated at run-time) */
115 .globl FIQ_STACK_START
120 /* IRQ stack memory (calculated at run-time) + 8 bytes */
121 .globl IRQ_STACK_START_IN
126 * the actual reset code
131 * set the cpu to SVC32 mode
139 * we do sys-critical inits only at reboot,
140 * not when booting from ram!
142 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
146 /* Set stackpointer in internal RAM to call board_init_f */
148 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
149 bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
153 /*------------------------------------------------------------------------------*/
156 * void relocate_code (addr_sp, gd, addr_moni)
158 * This "function" does not return, instead it continues in RAM
159 * after relocating the monitor code.
164 mov r4, r0 /* save addr_sp */
165 mov r5, r1 /* save addr of gd */
166 mov r6, r2 /* save addr of destination */
168 /* Set up the stack */
174 moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
175 beq clear_bss /* skip relocation */
176 mov r1, r6 /* r1 <- scratch for copy_loop */
177 ldr r3, _bss_start_ofs
178 add r2, r0, r3 /* r2 <- source end address */
181 ldmia r0!, {r9-r10} /* copy from source address [r0] */
182 stmia r1!, {r9-r10} /* copy to target address [r1] */
183 cmp r0, r2 /* until source end address [r2] */
186 #ifndef CONFIG_SPL_BUILD
188 * fix .rel.dyn relocations
190 ldr r0, _TEXT_BASE /* r0 <- Text base */
191 sub r9, r6, r0 /* r9 <- relocation offset */
192 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
193 add r10, r10, r0 /* r10 <- sym table in FLASH */
194 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
195 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
196 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
197 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
199 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
200 add r0, r0, r9 /* r0 <- location to fix up in RAM */
203 cmp r7, #23 /* relative fixup? */
205 cmp r7, #2 /* absolute fixup? */
207 /* ignore unknown type of fixup */
210 /* absolute fix: set location to (offset) symbol value */
211 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
212 add r1, r10, r1 /* r1 <- address of symbol in table */
213 ldr r1, [r1, #4] /* r1 <- symbol value */
214 add r1, r1, r9 /* r1 <- relocated sym addr */
217 /* relative fix: increase location by offset */
222 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
228 #ifndef CONFIG_SPL_BUILD
229 ldr r0, _bss_start_ofs
231 mov r4, r6 /* reloc addr */
234 mov r2, #0x00000000 /* clear */
236 clbss_l:cmp r0, r1 /* clear loop... */
237 bhs clbss_e /* if reached end of bss, exit */
248 * We are done. Do not return, instead branch to second part of board
249 * initialization, now running from RAM.
251 #ifdef CONFIG_NAND_SPL
252 ldr r0, _nand_boot_ofs
258 ldr r0, _board_init_r_ofs
262 /* setup parameters for board_init_r */
263 mov r0, r5 /* gd_t */
264 mov r1, r6 /* dest_addr */
269 .word board_init_r - _start
273 .word __rel_dyn_start - _start
275 .word __rel_dyn_end - _start
277 .word __dynsym_start - _start
280 *************************************************************************
282 * CPU_init_critical registers
284 * setup important registers
285 * setup memory timing
287 *************************************************************************
290 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
292 /* arm_int_generic assumes the ARM boot monitor, or user software,
293 * has initialized the platform
295 mov pc, lr /* back to my caller */
298 *************************************************************************
302 *************************************************************************
308 #define S_FRAME_SIZE 72
330 #define MODE_SVC 0x13
334 * use bad_save_user_regs for abort/prefetch/undef/swi ...
335 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
338 .macro bad_save_user_regs
339 @ carve out a frame on current user stack
340 sub sp, sp, #S_FRAME_SIZE
341 stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
343 ldr r2, IRQ_STACK_START_IN
344 @ get values for "aborted" pc and cpsr (into parm regs)
346 add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
349 stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
350 mov r0, sp @ save current stack into r0 (param register)
353 .macro irq_save_user_regs
354 sub sp, sp, #S_FRAME_SIZE
355 stmia sp, {r0 - r12} @ Calling r0-r12
356 @ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
358 stmdb r8, {sp, lr}^ @ Calling SP, LR
359 str lr, [r8, #0] @ Save calling PC
361 str r6, [r8, #4] @ Save CPSR
362 str r0, [r8, #8] @ Save OLD_R0
366 .macro irq_restore_user_regs
367 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
369 ldr lr, [sp, #S_PC] @ Get PC
370 add sp, sp, #S_FRAME_SIZE
371 subs pc, lr, #4 @ return & move spsr_svc into cpsr
375 ldr r13, IRQ_STACK_START_IN @ setup our mode stack
377 str lr, [r13] @ save caller lr in position 0 of saved stack
378 mrs lr, spsr @ get the spsr
379 str lr, [r13, #4] @ save spsr in position 1 of saved stack
380 mov r13, #MODE_SVC @ prepare SVC-Mode
382 msr spsr, r13 @ switch modes, make sure moves will execute
383 mov lr, pc @ capture return pc
384 movs pc, lr @ jump to next instruction & switch modes.
387 .macro get_irq_stack @ setup IRQ stack
388 ldr sp, IRQ_STACK_START
391 .macro get_fiq_stack @ setup FIQ stack
392 ldr sp, FIQ_STACK_START
399 .globl undefined_instruction
400 undefined_instruction:
403 bl do_undefined_instruction
406 .globl software_interrupt
410 bl do_software_interrupt
413 .globl prefetch_abort
433 #ifdef CONFIG_USE_IRQ
440 irq_restore_user_regs
446 /* someone ought to write a more effiction fiq_save_user_regs */
449 irq_restore_user_regs