git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/am33xx/ddr.c

   1 /*
   2  * DDR Configuration for AM33xx devices.
   3  *
   4  * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/cpu.h>
  10 #include <asm/arch/ddr_defs.h>
  11 #include <asm/arch/sys_proto.h>
  12 #include <asm/io.h>
  13 #include <asm/emif.h>
  14
  15 /**
  16  * Base address for EMIF instances
  17  */
  18 static struct emif_reg_struct *emif_reg[2] = {
  19                                 (struct emif_reg_struct *)EMIF4_0_CFG_BASE,
  20                                 (struct emif_reg_struct *)EMIF4_1_CFG_BASE};
  21
  22 /**
  23  * Base addresses for DDR PHY cmd/data regs
  24  */
  25 static struct ddr_cmd_regs *ddr_cmd_reg[2] = {
  26                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR,
  27                                 (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2};
  28
  29 static struct ddr_data_regs *ddr_data_reg[2] = {
  30                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR,
  31                                 (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2};
  32
  33 /**
  34  * Base address for ddr io control instances
  35  */
  36 static struct ddr_cmdtctrl *ioctrl_reg = {
  37                         (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
  38
  39 static inline u32 get_mr(int nr, u32 cs, u32 mr_addr)
  40 {
  41         u32 mr;
  42
  43         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  44         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  45
  46         mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data);
  47         debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr);
  48         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  49             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  50             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  51                 return mr & 0xff;
  52         else
  53                 return mr;
  54 }
  55
  56 static inline void set_mr(int nr, u32 cs, u32 mr_addr, u32 mr_val)
  57 {
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif_reg[nr]->emif_lpddr2_mode_reg_cfg);
  60         writel(mr_val, &emif_reg[nr]->emif_lpddr2_mode_reg_data);
  61 }
  62
  63 static void configure_mr(int nr, u32 cs)
  64 {
  65         u32 mr_addr;
  66
  67         while (get_mr(nr, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
  68                 ;
  69         set_mr(nr, cs, LPDDR2_MR10, 0x56);
  70
  71         set_mr(nr, cs, LPDDR2_MR1, 0x43);
  72         set_mr(nr, cs, LPDDR2_MR2, 0x2);
  73
  74         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
  75         set_mr(nr, cs, mr_addr, 0x2);
  76 }
  77
  78 /*
  79  * Configure EMIF4D5 registers and MR registers
  80  */
  81 void config_sdram_emif4d5(const struct emif_regs *regs, int nr)
  82 {
  83         writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl);
  84         writel(0x0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw);
  85         writel(0x1, &emif_reg[nr]->emif_iodft_tlgc);
  86         writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
  87
  88         writel(regs->temp_alert_config, &emif_reg[nr]->emif_temp_alert_config);
  89         writel(regs->emif_rd_wr_lvl_rmp_win,
  90                &emif_reg[nr]->emif_rd_wr_lvl_rmp_win);
  91         writel(regs->emif_rd_wr_lvl_rmp_ctl,
  92                &emif_reg[nr]->emif_rd_wr_lvl_rmp_ctl);
  93         writel(regs->emif_rd_wr_lvl_ctl, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
  94         writel(regs->emif_rd_wr_exec_thresh,
  95                &emif_reg[nr]->emif_rd_wr_exec_thresh);
  96
  97         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
  98         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
  99
 100         configure_mr(nr, 0);
 101         configure_mr(nr, 1);
 102 }
 103
 104 /**
 105  * Configure SDRAM
 106  */
 107 void config_sdram(const struct emif_regs *regs, int nr)
 108 {
 109         if (regs->zq_config) {
 110                 /*
 111                  * A value of 0x2800 for the REF CTRL will give us
 112                  * about 570us for a delay, which will be long enough
 113                  * to configure things.
 114                  */
 115                 writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl);
 116                 writel(regs->zq_config, &emif_reg[nr]->emif_zq_config);
 117                 writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
 118                 writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 119                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 120                 writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 121         }
 122         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl);
 123         writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
 124         writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config);
 125 }
 126
 127 /**
 128  * Set SDRAM timings
 129  */
 130 void set_sdram_timings(const struct emif_regs *regs, int nr)
 131 {
 132         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1);
 133         writel(regs->sdram_tim1, &emif_reg[nr]->emif_sdram_tim_1_shdw);
 134         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2);
 135         writel(regs->sdram_tim2, &emif_reg[nr]->emif_sdram_tim_2_shdw);
 136         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3);
 137         writel(regs->sdram_tim3, &emif_reg[nr]->emif_sdram_tim_3_shdw);
 138 }
 139
 140 void __weak emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size)
 141 {
 142 }
 143
 144 /*
 145  * Configure EXT PHY registers
 146  */
 147 static void ext_phy_settings(const struct emif_regs *regs, int nr)
 148 {
 149         u32 *ext_phy_ctrl_base = 0;
 150         u32 *emif_ext_phy_ctrl_base = 0;
 151         const u32 *ext_phy_ctrl_const_regs;
 152         u32 i = 0;
 153         u32 size;
 154
 155         ext_phy_ctrl_base = (u32 *)&(regs->emif_ddr_ext_phy_ctrl_1);
 156         emif_ext_phy_ctrl_base =
 157                         (u32 *)&(emif_reg[nr]->emif_ddr_ext_phy_ctrl_1);
 158
 159         /* Configure external phy control timing registers */
 160         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 161                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 162                 /* Update shadow registers */
 163                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 164         }
 165
 166         /*
 167          * external phy 6-24 registers do not change with
 168          * ddr frequency
 169          */
 170         emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs, &size);
 171
 172         if (!size)
 173                 return;
 174
 175         for (i = 0; i < size; i++) {
 176                 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 177                 /* Update shadow registers */
 178                 writel(ext_phy_ctrl_const_regs[i], emif_ext_phy_ctrl_base++);
 179         }
 180 }
 181
 182 /**
 183  * Configure DDR PHY
 184  */
 185 void config_ddr_phy(const struct emif_regs *regs, int nr)
 186 {
 187         /*
 188          * disable initialization and refreshes for now until we
 189          * finish programming EMIF regs.
 190          */
 191         setbits_le32(&emif_reg[nr]->emif_sdram_ref_ctrl,
 192                      EMIF_REG_INITREF_DIS_MASK);
 193
 194         writel(regs->emif_ddr_phy_ctlr_1,
 195                 &emif_reg[nr]->emif_ddr_phy_ctrl_1);
 196         writel(regs->emif_ddr_phy_ctlr_1,
 197                 &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw);
 198
 199         if (get_emif_rev((u32)emif_reg[nr]) == EMIF_4D5)
 200                 ext_phy_settings(regs, nr);
 201 }
 202
 203 /**
 204  * Configure DDR CMD control registers
 205  */
 206 void config_cmd_ctrl(const struct cmd_control *cmd, int nr)
 207 {
 208         if (!cmd)
 209                 return;
 210
 211         writel(cmd->cmd0csratio, &ddr_cmd_reg[nr]->cm0csratio);
 212         writel(cmd->cmd0iclkout, &ddr_cmd_reg[nr]->cm0iclkout);
 213
 214         writel(cmd->cmd1csratio, &ddr_cmd_reg[nr]->cm1csratio);
 215         writel(cmd->cmd1iclkout, &ddr_cmd_reg[nr]->cm1iclkout);
 216
 217         writel(cmd->cmd2csratio, &ddr_cmd_reg[nr]->cm2csratio);
 218         writel(cmd->cmd2iclkout, &ddr_cmd_reg[nr]->cm2iclkout);
 219 }
 220
 221 /**
 222  * Configure DDR DATA registers
 223  */
 224 void config_ddr_data(const struct ddr_data *data, int nr)
 225 {
 226         int i;
 227
 228         if (!data)
 229                 return;
 230
 231         for (i = 0; i < DDR_DATA_REGS_NR; i++) {
 232                 writel(data->datardsratio0,
 233                         &(ddr_data_reg[nr]+i)->dt0rdsratio0);
 234                 writel(data->datawdsratio0,
 235                         &(ddr_data_reg[nr]+i)->dt0wdsratio0);
 236                 writel(data->datawiratio0,
 237                         &(ddr_data_reg[nr]+i)->dt0wiratio0);
 238                 writel(data->datagiratio0,
 239                         &(ddr_data_reg[nr]+i)->dt0giratio0);
 240                 writel(data->datafwsratio0,
 241                         &(ddr_data_reg[nr]+i)->dt0fwsratio0);
 242                 writel(data->datawrsratio0,
 243                         &(ddr_data_reg[nr]+i)->dt0wrsratio0);
 244         }
 245 }
 246
 247 void config_io_ctrl(const struct ctrl_ioregs *ioregs)
 248 {
 249         if (!ioregs)
 250                 return;
 251
 252         writel(ioregs->cm0ioctl, &ioctrl_reg->cm0ioctl);
 253         writel(ioregs->cm1ioctl, &ioctrl_reg->cm1ioctl);
 254         writel(ioregs->cm2ioctl, &ioctrl_reg->cm2ioctl);
 255         writel(ioregs->dt0ioctl, &ioctrl_reg->dt0ioctl);
 256         writel(ioregs->dt1ioctl, &ioctrl_reg->dt1ioctl);
 257 #ifdef CONFIG_AM43XX
 258         writel(ioregs->dt2ioctrl, &ioctrl_reg->dt2ioctrl);
 259         writel(ioregs->dt3ioctrl, &ioctrl_reg->dt3ioctrl);
 260         writel(ioregs->emif_sdram_config_ext,
 261                &ioctrl_reg->emif_sdram_config_ext);
 262 #endif
 263 }