4 * AM33XX emif4 configuration file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <asm/arch/cpu.h>
21 #include <asm/arch/ddr_defs.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/sys_proto.h>
28 DECLARE_GLOBAL_DATA_PTR;
32 /* dram_init must store complete ramsize in gd->ram_size */
33 gd->ram_size = get_ram_size(
34 (void *)CONFIG_SYS_SDRAM_BASE,
35 CONFIG_MAX_RAM_BANK_SIZE);
39 void dram_init_banksize(void)
41 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
42 gd->bd->bi_dram[0].size = gd->ram_size;
46 #ifdef CONFIG_SPL_BUILD
47 static struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
48 static struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
50 static const struct ddr_data ddr2_data = {
51 .datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
52 |(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0)),
53 .datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
54 |(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0)),
55 .datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
56 |(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0)),
57 .datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
58 |(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0)),
59 .datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
60 |(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0)),
61 .datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
62 |(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0)),
63 .datauserank0delay = DDR2_PHY_RANK0_DELAY,
64 .datadldiff0 = PHY_DLL_LOCK_DIFF,
67 static const struct cmd_control ddr2_cmd_ctrl_data = {
68 .cmd0csratio = DDR2_RATIO,
69 .cmd0dldiff = DDR2_DLL_LOCK_DIFF,
70 .cmd0iclkout = DDR2_INVERT_CLKOUT,
72 .cmd1csratio = DDR2_RATIO,
73 .cmd1dldiff = DDR2_DLL_LOCK_DIFF,
74 .cmd1iclkout = DDR2_INVERT_CLKOUT,
76 .cmd2csratio = DDR2_RATIO,
77 .cmd2dldiff = DDR2_DLL_LOCK_DIFF,
78 .cmd2iclkout = DDR2_INVERT_CLKOUT,
81 static const struct emif_regs ddr2_emif_reg_data = {
82 .sdram_config = DDR2_EMIF_SDCFG,
83 .ref_ctrl = DDR2_EMIF_SDREF,
84 .sdram_tim1 = DDR2_EMIF_TIM1,
85 .sdram_tim2 = DDR2_EMIF_TIM2,
86 .sdram_tim3 = DDR2_EMIF_TIM3,
87 .emif_ddr_phy_ctlr_1 = DDR2_EMIF_READ_LATENCY,
90 static const struct ddr_data ddr3_data = {
91 .datardsratio0 = DDR3_RD_DQS,
92 .datawdsratio0 = DDR3_WR_DQS,
93 .datafwsratio0 = DDR3_PHY_FIFO_WE,
94 .datawrsratio0 = DDR3_PHY_WR_DATA,
95 .datadldiff0 = PHY_DLL_LOCK_DIFF,
98 static const struct cmd_control ddr3_cmd_ctrl_data = {
99 .cmd0csratio = DDR3_RATIO,
100 .cmd0dldiff = DDR3_DLL_LOCK_DIFF,
101 .cmd0iclkout = DDR3_INVERT_CLKOUT,
103 .cmd1csratio = DDR3_RATIO,
104 .cmd1dldiff = DDR3_DLL_LOCK_DIFF,
105 .cmd1iclkout = DDR3_INVERT_CLKOUT,
107 .cmd2csratio = DDR3_RATIO,
108 .cmd2dldiff = DDR3_DLL_LOCK_DIFF,
109 .cmd2iclkout = DDR3_INVERT_CLKOUT,
112 static struct emif_regs ddr3_emif_reg_data = {
113 .sdram_config = DDR3_EMIF_SDCFG,
114 .ref_ctrl = DDR3_EMIF_SDREF,
115 .sdram_tim1 = DDR3_EMIF_TIM1,
116 .sdram_tim2 = DDR3_EMIF_TIM2,
117 .sdram_tim3 = DDR3_EMIF_TIM3,
118 .zq_config = DDR3_ZQ_CFG,
119 .emif_ddr_phy_ctlr_1 = DDR3_EMIF_READ_LATENCY,
122 static void config_vtp(void)
124 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
125 &vtpreg->vtp0ctrlreg);
126 writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
127 &vtpreg->vtp0ctrlreg);
128 writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
129 &vtpreg->vtp0ctrlreg);
132 while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
137 void config_ddr(short ddr_type)
139 int ddr_pll, ioctrl_val;
140 const struct emif_regs *emif_regs;
141 const struct ddr_data *ddr_data;
142 const struct cmd_control *cmd_ctrl_data;
144 if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR2) {
146 cmd_ctrl_data = &ddr2_cmd_ctrl_data;
147 ddr_data = &ddr2_data;
148 ioctrl_val = DDR2_IOCTRL_VALUE;
149 emif_regs = &ddr2_emif_reg_data;
150 } else if (ddr_type == EMIF_REG_SDRAM_TYPE_DDR3) {
152 cmd_ctrl_data = &ddr3_cmd_ctrl_data;
153 ddr_data = &ddr3_data;
154 ioctrl_val = DDR3_IOCTRL_VALUE;
155 emif_regs = &ddr3_emif_reg_data;
157 puts("Unknown memory type");
161 enable_emif_clocks();
162 ddr_pll_config(ddr_pll);
164 config_cmd_ctrl(cmd_ctrl_data);
166 config_ddr_data(0, ddr_data);
167 config_ddr_data(1, ddr_data);
169 config_io_ctrl(ioctrl_val);
171 /* Set CKE to be controlled by EMIF/DDR PHY */
172 writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl);
174 /* Program EMIF instance */
175 config_ddr_phy(emif_regs);
176 set_sdram_timings(emif_regs);
177 config_sdram(emif_regs);