2 * Copyright 2013 Broadcom Corporation.
4 * SPDX-License-Identifier: GPL-2.0+
9 * bcm281xx-specific clock tables
15 #include <asm/errno.h>
16 #include <asm/arch/sysmap.h>
17 #include <asm/kona-common/clk.h>
21 #define CLOCK_1M (CLOCK_1K * 1000)
23 /* declare a reference clock */
24 #define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
25 static struct refclk clk_name = { \
28 .parent = clk_parent, \
31 .ops = &ref_clk_ops, \
39 /* Declare a list of reference clocks */
40 DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
41 DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
42 DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
43 DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
44 DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
45 DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
46 DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
47 DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
48 DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
49 DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
50 DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
53 struct refclk *procclk;
57 /* Lookup table for string to clk tranlation */
58 #define MKSTR(x) {&x, #x}
59 static struct refclk_lkup refclk_str_tbl[] = {
60 MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
61 MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
62 MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
63 MKSTR(var_52m), MKSTR(var_13m),
66 int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
68 /* convert ref clock string to clock structure pointer */
69 struct refclk *refclk_str_to_clk(const char *name)
72 struct refclk_lkup *tblp = refclk_str_tbl;
73 for (i = 0; i < refclk_entries; i++, tblp++) {
74 if (!(strcmp(name, tblp->name)))
80 /* frequency tables indexed by freq_id */
81 unsigned long master_axi_freq_tbl[8] = {
92 unsigned long master_ahb_freq_tbl[8] = {
103 unsigned long slave_axi_freq_tbl[8] = {
112 unsigned long slave_apb_freq_tbl[8] = {
121 unsigned long esub_freq_tbl[8] = {
131 static struct bus_clk_data bsc1_apb_data = {
132 .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
135 static struct bus_clk_data bsc2_apb_data = {
136 .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
139 static struct bus_clk_data bsc3_apb_data = {
140 .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
143 /* * Master CCU clocks */
144 static struct peri_clk_data sdio1_data = {
145 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
146 .clocks = CLOCKS("ref_crystal",
151 .sel = SELECTOR(0x0a28, 0, 3),
152 .div = DIVIDER(0x0a28, 4, 14),
153 .trig = TRIGGER(0x0afc, 9),
156 static struct peri_clk_data sdio2_data = {
157 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
158 .clocks = CLOCKS("ref_crystal",
163 .sel = SELECTOR(0x0a2c, 0, 3),
164 .div = DIVIDER(0x0a2c, 4, 14),
165 .trig = TRIGGER(0x0afc, 10),
168 static struct peri_clk_data sdio3_data = {
169 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
170 .clocks = CLOCKS("ref_crystal",
175 .sel = SELECTOR(0x0a34, 0, 3),
176 .div = DIVIDER(0x0a34, 4, 14),
177 .trig = TRIGGER(0x0afc, 12),
180 static struct peri_clk_data sdio4_data = {
181 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
182 .clocks = CLOCKS("ref_crystal",
187 .sel = SELECTOR(0x0a30, 0, 3),
188 .div = DIVIDER(0x0a30, 4, 14),
189 .trig = TRIGGER(0x0afc, 11),
192 static struct peri_clk_data sdio1_sleep_data = {
193 .clocks = CLOCKS("ref_32k"),
194 .gate = SW_ONLY_GATE(0x0358, 20, 4),
197 static struct peri_clk_data sdio2_sleep_data = {
198 .clocks = CLOCKS("ref_32k"),
199 .gate = SW_ONLY_GATE(0x035c, 20, 4),
202 static struct peri_clk_data sdio3_sleep_data = {
203 .clocks = CLOCKS("ref_32k"),
204 .gate = SW_ONLY_GATE(0x0364, 20, 4),
207 static struct peri_clk_data sdio4_sleep_data = {
208 .clocks = CLOCKS("ref_32k"),
209 .gate = SW_ONLY_GATE(0x0360, 20, 4),
212 static struct bus_clk_data sdio1_ahb_data = {
213 .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
216 static struct bus_clk_data sdio2_ahb_data = {
217 .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
220 static struct bus_clk_data sdio3_ahb_data = {
221 .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
224 static struct bus_clk_data sdio4_ahb_data = {
225 .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
228 /* * Slave CCU clocks */
229 static struct peri_clk_data bsc1_data = {
230 .gate = HW_SW_GATE(0x0458, 18, 2, 3),
231 .clocks = CLOCKS("ref_crystal",
236 .sel = SELECTOR(0x0a64, 0, 3),
237 .trig = TRIGGER(0x0afc, 23),
240 static struct peri_clk_data bsc2_data = {
241 .gate = HW_SW_GATE(0x045c, 18, 2, 3),
242 .clocks = CLOCKS("ref_crystal",
247 .sel = SELECTOR(0x0a68, 0, 3),
248 .trig = TRIGGER(0x0afc, 24),
251 static struct peri_clk_data bsc3_data = {
252 .gate = HW_SW_GATE(0x0484, 18, 2, 3),
253 .clocks = CLOCKS("ref_crystal",
258 .sel = SELECTOR(0x0a84, 0, 3),
259 .trig = TRIGGER(0x0b00, 2),
266 static struct ccu_clock kpm_ccu_clk = {
268 .name = "kpm_ccu_clk",
270 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
272 .num_policy_masks = 1,
273 .policy_freq_offset = 0x00000008,
275 .policy_ctl_offset = 0x0000000c,
276 .policy0_mask_offset = 0x00000010,
277 .policy1_mask_offset = 0x00000014,
278 .policy2_mask_offset = 0x00000018,
279 .policy3_mask_offset = 0x0000001c,
280 .lvm_en_offset = 0x00000034,
282 .freq_tbl = master_axi_freq_tbl,
285 static struct ccu_clock kps_ccu_clk = {
287 .name = "kps_ccu_clk",
289 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
291 .num_policy_masks = 2,
292 .policy_freq_offset = 0x00000008,
294 .policy_ctl_offset = 0x0000000c,
295 .policy0_mask_offset = 0x00000010,
296 .policy1_mask_offset = 0x00000014,
297 .policy2_mask_offset = 0x00000018,
298 .policy3_mask_offset = 0x0000001c,
299 .policy0_mask2_offset = 0x00000048,
300 .policy1_mask2_offset = 0x0000004c,
301 .policy2_mask2_offset = 0x00000050,
302 .policy3_mask2_offset = 0x00000054,
303 .lvm_en_offset = 0x00000034,
305 .freq_tbl = slave_axi_freq_tbl,
308 #ifdef CONFIG_BCM_SF2_ETH
309 static struct ccu_clock esub_ccu_clk = {
311 .name = "esub_ccu_clk",
313 .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
315 .num_policy_masks = 1,
316 .policy_freq_offset = 0x00000008,
318 .policy_ctl_offset = 0x0000000c,
319 .policy0_mask_offset = 0x00000010,
320 .policy1_mask_offset = 0x00000014,
321 .policy2_mask_offset = 0x00000018,
322 .policy3_mask_offset = 0x0000001c,
323 .lvm_en_offset = 0x00000034,
325 .freq_tbl = esub_freq_tbl,
334 static struct bus_clock sdio1_ahb_clk = {
336 .name = "sdio1_ahb_clk",
337 .parent = &kpm_ccu_clk.clk,
339 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
341 .freq_tbl = master_ahb_freq_tbl,
342 .data = &sdio1_ahb_data,
345 static struct bus_clock sdio2_ahb_clk = {
347 .name = "sdio2_ahb_clk",
348 .parent = &kpm_ccu_clk.clk,
350 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
352 .freq_tbl = master_ahb_freq_tbl,
353 .data = &sdio2_ahb_data,
356 static struct bus_clock sdio3_ahb_clk = {
358 .name = "sdio3_ahb_clk",
359 .parent = &kpm_ccu_clk.clk,
361 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
363 .freq_tbl = master_ahb_freq_tbl,
364 .data = &sdio3_ahb_data,
367 static struct bus_clock sdio4_ahb_clk = {
369 .name = "sdio4_ahb_clk",
370 .parent = &kpm_ccu_clk.clk,
372 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
374 .freq_tbl = master_ahb_freq_tbl,
375 .data = &sdio4_ahb_data,
378 static struct bus_clock bsc1_apb_clk = {
380 .name = "bsc1_apb_clk",
381 .parent = &kps_ccu_clk.clk,
383 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
385 .freq_tbl = slave_apb_freq_tbl,
386 .data = &bsc1_apb_data,
389 static struct bus_clock bsc2_apb_clk = {
391 .name = "bsc2_apb_clk",
392 .parent = &kps_ccu_clk.clk,
394 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
396 .freq_tbl = slave_apb_freq_tbl,
397 .data = &bsc2_apb_data,
400 static struct bus_clock bsc3_apb_clk = {
402 .name = "bsc3_apb_clk",
403 .parent = &kps_ccu_clk.clk,
405 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
407 .freq_tbl = slave_apb_freq_tbl,
408 .data = &bsc3_apb_data,
412 static struct peri_clock sdio1_clk = {
415 .parent = &ref_52m.clk,
416 .ops = &peri_clk_ops,
417 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
422 static struct peri_clock sdio2_clk = {
425 .parent = &ref_52m.clk,
426 .ops = &peri_clk_ops,
427 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
432 static struct peri_clock sdio3_clk = {
435 .parent = &ref_52m.clk,
436 .ops = &peri_clk_ops,
437 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
442 static struct peri_clock sdio4_clk = {
445 .parent = &ref_52m.clk,
446 .ops = &peri_clk_ops,
447 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
452 static struct peri_clock sdio1_sleep_clk = {
454 .name = "sdio1_sleep_clk",
455 .parent = &kpm_ccu_clk.clk,
457 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
459 .data = &sdio1_sleep_data,
462 static struct peri_clock sdio2_sleep_clk = {
464 .name = "sdio2_sleep_clk",
465 .parent = &kpm_ccu_clk.clk,
467 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
469 .data = &sdio2_sleep_data,
472 static struct peri_clock sdio3_sleep_clk = {
474 .name = "sdio3_sleep_clk",
475 .parent = &kpm_ccu_clk.clk,
477 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
479 .data = &sdio3_sleep_data,
482 static struct peri_clock sdio4_sleep_clk = {
484 .name = "sdio4_sleep_clk",
485 .parent = &kpm_ccu_clk.clk,
487 .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
489 .data = &sdio4_sleep_data,
492 /* KPS peripheral clock */
493 static struct peri_clock bsc1_clk = {
496 .parent = &ref_13m.clk,
497 .rate = 13 * CLOCK_1M,
499 .ops = &peri_clk_ops,
500 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
505 static struct peri_clock bsc2_clk = {
508 .parent = &ref_13m.clk,
509 .rate = 13 * CLOCK_1M,
511 .ops = &peri_clk_ops,
512 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
517 static struct peri_clock bsc3_clk = {
520 .parent = &ref_13m.clk,
521 .rate = 13 * CLOCK_1M,
523 .ops = &peri_clk_ops,
524 .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
529 /* public table for registering clocks */
530 struct clk_lookup arch_clk_tbl[] = {
531 /* Peripheral clocks */
551 #ifdef CONFIG_BCM_SF2_ETH
556 /* public array size */
557 unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);