1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2013 Broadcom Corporation.
8 * bcm281xx architecture clock framework
14 #include <linux/errno.h>
16 #include <asm/arch/sysmap.h>
17 #include <asm/kona-common/clk.h>
20 #define CLK_WR_ACCESS_PASSWORD 0x00a5a501
21 #define WR_ACCESS_OFFSET 0 /* common to all clock blocks */
22 #define POLICY_CTL_GO 1 /* Load and refresh policy masks */
23 #define POLICY_CTL_GO_ATL 4 /* Active Load */
26 int clk_get_and_enable(char *clkstr)
31 debug("%s: %s\n", __func__, clkstr);
39 printf("%s: Couldn't find %s\n", __func__, clkstr);
46 * Poll a register in a CCU's address space, returning when the
47 * specified bit in that register's value is set (or clear). Delay
48 * a microsecond after each read of the register. Returns true if
49 * successful, or false if we gave up trying.
51 * Caller must ensure the CCU lock is held.
53 #define CLK_GATE_DELAY_USEC 2000
54 static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
57 u32 bit_mask = 1 << bit;
59 for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
63 val = readl(base + offset);
64 bit_val = (val & bit_mask) ? 1 : 0;
66 return 0; /* success */
70 debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
71 __func__, base + offset, bit, want);
76 /* Enable a peripheral clock */
77 static int peri_clk_enable(struct clk *c, int enable)
81 struct peri_clock *peri_clk = to_peri_clk(c);
82 struct peri_clk_data *cd = peri_clk->data;
83 struct bcm_clk_gate *gate = &cd->gate;
84 void *base = (void *)c->ccu_clk_mgr_base;
87 debug("%s: %s\n", __func__, c->name);
89 clk_get_rate(c); /* Make sure rate and sel are filled in */
92 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
95 debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
96 __func__, c->name, c->rate, c->div, c->sel,
100 * clkgate - only software controllable gates are
101 * supported by u-boot which includes all clocks
102 * that matter. This avoids bringing in a lot of extra
103 * complexity as done in the kernel framework.
105 if (gate_exists(gate)) {
106 reg = readl(base + cd->gate.offset);
107 reg |= (1 << cd->gate.en_bit);
108 writel(reg, base + cd->gate.offset);
111 /* div and pll select */
112 if (divider_exists(&cd->div)) {
113 reg = readl(base + cd->div.offset);
114 bitfield_replace(reg, cd->div.shift, cd->div.width,
116 writel(reg, base + cd->div.offset);
119 /* frequency selector */
120 if (selector_exists(&cd->sel)) {
121 reg = readl(base + cd->sel.offset);
122 bitfield_replace(reg, cd->sel.shift, cd->sel.width,
124 writel(reg, base + cd->sel.offset);
128 if (trigger_exists(&cd->trig)) {
129 writel((1 << cd->trig.bit), base + cd->trig.offset);
131 /* wait for trigger status bit to go to 0 */
132 ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
137 /* wait for running (status_bit = 1) */
138 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
142 debug("%s disable clock %s\n", __func__, c->name);
145 reg = readl(base + cd->gate.offset);
146 reg &= ~(1 << cd->gate.en_bit);
147 writel(reg, base + cd->gate.offset);
149 /* wait for stop (status_bit = 0) */
150 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
154 writel(0, base + WR_ACCESS_OFFSET);
159 /* Set the rate of a peripheral clock */
160 static int peri_clk_set_rate(struct clk *c, unsigned long rate)
165 unsigned long new_rate = 0, div = 1;
166 struct peri_clock *peri_clk = to_peri_clk(c);
167 struct peri_clk_data *cd = peri_clk->data;
170 debug("%s: %s\n", __func__, c->name);
174 for (clock = cd->clocks; *clock; clock++, i++) {
175 struct refclk *ref = refclk_str_to_clk(*clock);
177 printf("%s: Lookup of %s failed\n", __func__, *clock);
181 /* round to the new rate */
182 div = ref->clk.rate / rate;
186 new_rate = ref->clk.rate / div;
188 /* get the min diff */
189 if (abs(new_rate - rate) < diff) {
190 diff = abs(new_rate - rate);
192 c->parent = &ref->clk;
198 debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
199 c->name, c->rate, c->div, c->sel, c->parent->rate);
203 /* Get the rate of a peripheral clock */
204 static unsigned long peri_clk_get_rate(struct clk *c)
206 struct peri_clock *peri_clk = to_peri_clk(c);
207 struct peri_clk_data *cd = peri_clk->data;
208 void *base = (void *)c->ccu_clk_mgr_base;
214 debug("%s: %s\n", __func__, c->name);
215 if (selector_exists(&cd->sel)) {
216 reg = readl(base + cd->sel.offset);
217 c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
220 * For peri clocks that don't have a selector, the single
221 * reference clock will always exist at index 0.
226 if (divider_exists(&cd->div)) {
227 reg = readl(base + cd->div.offset);
228 div = bitfield_extract(reg, cd->div.shift, cd->div.width);
233 ref = refclk_str_to_clk(clock[c->sel]);
235 printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
239 c->parent = &ref->clk;
241 c->rate = c->parent->rate / c->div;
242 debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
243 c->parent->rate, div, c->sel, c->rate);
248 /* Peripheral clock operations */
249 struct clk_ops peri_clk_ops = {
250 .enable = peri_clk_enable,
251 .set_rate = peri_clk_set_rate,
252 .get_rate = peri_clk_get_rate,
255 /* Enable a CCU clock */
256 static int ccu_clk_enable(struct clk *c, int enable)
258 struct ccu_clock *ccu_clk = to_ccu_clk(c);
259 void *base = (void *)c->ccu_clk_mgr_base;
263 debug("%s: %s\n", __func__, c->name);
265 return -EINVAL; /* CCU clock cannot shutdown */
268 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
270 /* config enable for policy engine */
271 writel(1, base + ccu_clk->lvm_en_offset);
273 /* wait for bit to go to 0 */
274 ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
279 if (!ccu_clk->freq_bit_shift)
280 ccu_clk->freq_bit_shift = 8;
282 /* Set frequency id for each of the 4 policies */
283 reg = ccu_clk->freq_id |
284 (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
285 (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
286 (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
287 writel(reg, base + ccu_clk->policy_freq_offset);
289 /* enable all clock mask */
290 writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
291 writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
292 writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
293 writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
295 if (ccu_clk->num_policy_masks == 2) {
296 writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
297 writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
298 writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
299 writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
302 /* start policy engine */
303 reg = readl(base + ccu_clk->policy_ctl_offset);
304 reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
305 writel(reg, base + ccu_clk->policy_ctl_offset);
307 /* wait till started */
308 ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
313 writel(0, base + WR_ACCESS_OFFSET);
318 /* Get the CCU clock rate */
319 static unsigned long ccu_clk_get_rate(struct clk *c)
321 struct ccu_clock *ccu_clk = to_ccu_clk(c);
322 debug("%s: %s\n", __func__, c->name);
323 c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
327 /* CCU clock operations */
328 struct clk_ops ccu_clk_ops = {
329 .enable = ccu_clk_enable,
330 .get_rate = ccu_clk_get_rate,
333 /* Enable a bus clock */
334 static int bus_clk_enable(struct clk *c, int enable)
336 struct bus_clock *bus_clk = to_bus_clk(c);
337 struct bus_clk_data *cd = bus_clk->data;
338 void *base = (void *)c->ccu_clk_mgr_base;
342 debug("%s: %s\n", __func__, c->name);
344 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
347 reg = readl(base + cd->gate.offset);
348 if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
349 debug("%s already %s\n", c->name,
350 enable ? "enabled" : "disabled");
352 int want = (enable) ? 1 : 0;
353 reg |= (1 << cd->gate.hw_sw_sel_bit);
356 reg |= (1 << cd->gate.en_bit);
358 reg &= ~(1 << cd->gate.en_bit);
360 writel(reg, base + cd->gate.offset);
361 ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
368 writel(0, base + WR_ACCESS_OFFSET);
373 /* Get the rate of a bus clock */
374 static unsigned long bus_clk_get_rate(struct clk *c)
376 struct bus_clock *bus_clk = to_bus_clk(c);
377 struct ccu_clock *ccu_clk;
379 debug("%s: %s\n", __func__, c->name);
380 ccu_clk = to_ccu_clk(c->parent);
382 c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
383 c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
387 /* Bus clock operations */
388 struct clk_ops bus_clk_ops = {
389 .enable = bus_clk_enable,
390 .get_rate = bus_clk_get_rate,
393 /* Enable a reference clock */
394 static int ref_clk_enable(struct clk *c, int enable)
396 debug("%s: %s\n", __func__, c->name);
400 /* Reference clock operations */
401 struct clk_ops ref_clk_ops = {
402 .enable = ref_clk_enable,
406 * clk.h implementation follows
409 /* Initialize the clock framework */
412 debug("%s:\n", __func__);
416 /* Get a clock handle, give a name string */
417 struct clk *clk_get(const char *con_id)
420 struct clk_lookup *clk_tblp;
422 debug("%s: %s\n", __func__, con_id);
424 clk_tblp = arch_clk_tbl;
425 for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
426 if (clk_tblp->con_id) {
427 if (!con_id || strcmp(clk_tblp->con_id, con_id))
429 return clk_tblp->clk;
436 int clk_enable(struct clk *c)
440 debug("%s: %s\n", __func__, c->name);
441 if (!c->ops || !c->ops->enable)
444 /* enable parent clock first */
446 ret = clk_enable(c->parent);
453 ret = c->ops->enable(c, 1);
459 /* Disable a clock */
460 void clk_disable(struct clk *c)
462 debug("%s: %s\n", __func__, c->name);
463 if (!c->ops || !c->ops->enable)
468 c->ops->enable(c, 0);
473 clk_disable(c->parent);
476 /* Get the clock rate */
477 unsigned long clk_get_rate(struct clk *c)
481 if (!c || !c->ops || !c->ops->get_rate)
483 debug("%s: %s\n", __func__, c->name);
485 rate = c->ops->get_rate(c);
486 debug("%s: rate = %ld\n", __func__, rate);
490 /* Set the clock rate */
491 int clk_set_rate(struct clk *c, unsigned long rate)
495 if (!c || !c->ops || !c->ops->set_rate)
497 debug("%s: %s rate=%ld\n", __func__, c->name, rate);
502 ret = c->ops->set_rate(c, rate);
507 /* Not required for this arch */
509 long clk_round_rate(struct clk *clk, unsigned long rate);
510 int clk_set_parent(struct clk *clk, struct clk *parent);
511 struct clk *clk_get_parent(struct clk *clk);