2 * Copyright 2013 Broadcom Corporation.
4 * SPDX-License-Identifier: GPL-2.0+
7 #include <linux/stddef.h>
9 #ifdef CONFIG_CLK_DEBUG
12 static inline void writel(u32 val, void *addr)
14 printf("Write [0x%p] = 0x%08x\n", addr, val);
18 static inline u32 readl(void *addr)
20 u32 val = *(u32 *)addr;
21 printf("Read [0x%p] = 0x%08x\n", addr, val);
34 extern struct clk_lookup arch_clk_tbl[];
35 extern unsigned int arch_clk_tbl_array_size;
38 * struct clk_ops - standard clock operations
39 * @enable: enable/disable clock, see clk_enable() and clk_disable()
40 * @set_rate: set the clock rate, see clk_set_rate().
41 * @get_rate: get the clock rate, see clk_get_rate().
42 * @round_rate: round a given clock rate, see clk_round_rate().
43 * @set_parent: set the clock's parent, see clk_set_parent().
45 * Group the common clock implementations together so that we
46 * don't have to keep setting the same fiels again. We leave
47 * enable in struct clk.
51 int (*enable) (struct clk *c, int enable);
52 int (*set_rate) (struct clk *c, unsigned long rate);
53 unsigned long (*get_rate) (struct clk *c);
54 unsigned long (*round_rate) (struct clk *c, unsigned long rate);
55 int (*set_parent) (struct clk *c, struct clk *parent);
62 unsigned long rate; /* in HZ */
64 /* programmable divider. 0 means fixed ratio to parent clock */
70 unsigned long ccu_clk_mgr_base;
74 struct refclk *refclk_str_to_clk(const char *name);
76 #define U8_MAX ((u8)~0U)
77 #define U32_MAX ((u32)~0U)
78 #define U64_MAX ((u64)~0U)
80 /* The common clock framework uses u8 to represent a parent index */
81 #define PARENT_COUNT_MAX ((u32)U8_MAX)
83 #define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
84 #define BAD_CLK_NAME ((const char *)-1)
86 #define BAD_SCALED_DIV_VALUE U64_MAX
89 * Utility macros for object flag management. If possible, flags
90 * should be defined such that 0 is the desired default value.
92 #define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
93 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
94 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
95 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
96 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
98 /* Clock field state tests */
100 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
101 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
102 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
103 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
104 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
105 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
107 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
109 #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
110 #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
111 #define divider_has_fraction(div) (!divider_is_fixed(div) && \
112 (div)->frac_width > 0)
114 #define selector_exists(sel) ((sel)->width != 0)
115 #define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
117 /* Clock type, used to tell common block what it's part of */
119 bcm_clk_none, /* undefined clock type */
126 * Gating control and status is managed by a 32-bit gate register.
128 * There are several types of gating available:
130 * A clock with no gate is assumed to be always enabled.
131 * - hardware-only gating (auto-gating)
132 * Enabling or disabling clocks with this type of gate is
133 * managed automatically by the hardware. Such clocks can be
134 * considered by the software to be enabled. The current status
135 * of auto-gated clocks can be read from the gate status bit.
136 * - software-only gating
137 * Auto-gating is not available for this type of clock.
138 * Instead, software manages whether it's enabled by setting or
139 * clearing the enable bit. The current gate status of a gate
140 * under software control can be read from the gate status bit.
141 * To ensure a change to the gating status is complete, the
142 * status bit can be polled to verify that the gate has entered
144 * - selectable hardware or software gating
145 * Gating for this type of clock can be configured to be either
146 * under software or hardware control. Which type is in use is
147 * determined by the hw_sw_sel bit of the gate register.
149 struct bcm_clk_gate {
150 u32 offset; /* gate register offset */
151 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
152 u32 en_bit; /* 0: disable; 1: enable */
153 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
154 u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
159 * HW means this gate can be auto-gated
160 * SW means the state of this gate can be software controlled
161 * NO_DISABLE means this gate is (only) enabled if under software control
162 * SW_MANAGED means the status of this gate is under software control
163 * ENABLED means this software-managed gate is *supposed* to be enabled
165 #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
166 #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
167 #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
168 #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
169 #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
170 #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
173 * Gate initialization macros.
175 * Any gate initially under software control will be enabled.
178 /* A hardware/software gate initially under software control */
179 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
181 .offset = (_offset), \
182 .status_bit = (_status_bit), \
183 .en_bit = (_en_bit), \
184 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
185 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
186 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
187 FLAG(GATE, EXISTS), \
190 /* A hardware/software gate initially under hardware control */
191 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
193 .offset = (_offset), \
194 .status_bit = (_status_bit), \
195 .en_bit = (_en_bit), \
196 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
197 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
198 FLAG(GATE, EXISTS), \
201 /* A hardware-or-enabled gate (enabled if not under hardware control) */
202 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
204 .offset = (_offset), \
205 .status_bit = (_status_bit), \
206 .en_bit = (_en_bit), \
207 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
208 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
209 FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
212 /* A software-only gate */
213 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
215 .offset = (_offset), \
216 .status_bit = (_status_bit), \
217 .en_bit = (_en_bit), \
218 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
219 FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
222 /* A hardware-only gate */
223 #define HW_ONLY_GATE(_offset, _status_bit) \
225 .offset = (_offset), \
226 .status_bit = (_status_bit), \
227 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
231 * Each clock can have zero, one, or two dividers which change the
232 * output rate of the clock. Each divider can be either fixed or
233 * variable. If there are two dividers, they are the "pre-divider"
234 * and the "regular" or "downstream" divider. If there is only one,
235 * there is no pre-divider.
237 * A fixed divider is any non-zero (positive) value, and it
238 * indicates how the input rate is affected by the divider.
240 * The value of a variable divider is maintained in a sub-field of a
241 * 32-bit divider register. The position of the field in the
242 * register is defined by its offset and width. The value recorded
243 * in this field is always 1 less than the value it represents.
245 * In addition, a variable divider can indicate that some subset
246 * of its bits represent a "fractional" part of the divider. Such
247 * bits comprise the low-order portion of the divider field, and can
248 * be viewed as representing the portion of the divider that lies to
249 * the right of the decimal point. Most variable dividers have zero
250 * fractional bits. Variable dividers with non-zero fraction width
251 * still record a value 1 less than the value they represent; the
252 * added 1 does *not* affect the low-order bit in this case, it
253 * affects the bits above the fractional part only. (Often in this
254 * code a divider field value is distinguished from the value it
255 * represents by referring to the latter as a "divisor".)
257 * In order to avoid dealing with fractions, divider arithmetic is
258 * performed using "scaled" values. A scaled value is one that's
259 * been left-shifted by the fractional width of a divider. Dividing
260 * a scaled value by a scaled divisor produces the desired quotient
261 * without loss of precision and without any other special handling
264 * The recorded value of a variable divider can be modified. To
265 * modify either divider (or both), a clock must be enabled (i.e.,
266 * using its gate). In addition, a trigger register (described
267 * below) must be used to commit the change, and polled to verify
268 * the change is complete.
272 struct { /* variable divider */
273 u32 offset; /* divider register offset */
274 u32 shift; /* field shift */
275 u32 width; /* field width */
276 u32 frac_width; /* field fraction width */
278 u64 scaled_div; /* scaled divider value */
280 u32 fixed; /* non-zero fixed divider value */
282 u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
287 * EXISTS means this divider exists
288 * FIXED means it is a fixed-rate divider
290 #define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
291 #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
293 /* Divider initialization macros */
295 /* A fixed (non-zero) divider */
296 #define FIXED_DIVIDER(_value) \
299 .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
302 /* A divider with an integral divisor */
303 #define DIVIDER(_offset, _shift, _width) \
305 .offset = (_offset), \
308 .scaled_div = BAD_SCALED_DIV_VALUE, \
309 .flags = FLAG(DIV, EXISTS), \
312 /* A divider whose divisor has an integer and fractional part */
313 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
315 .offset = (_offset), \
318 .frac_width = (_frac_width), \
319 .scaled_div = BAD_SCALED_DIV_VALUE, \
320 .flags = FLAG(DIV, EXISTS), \
324 * Clocks may have multiple "parent" clocks. If there is more than
325 * one, a selector must be specified to define which of the parent
326 * clocks is currently in use. The selected clock is indicated in a
327 * sub-field of a 32-bit selector register. The range of
328 * representable selector values typically exceeds the number of
329 * available parent clocks. Occasionally the reset value of a
330 * selector field is explicitly set to a (specific) value that does
331 * not correspond to a defined input clock.
333 * We register all known parent clocks with the common clock code
334 * using a packed array (i.e., no empty slots) of (parent) clock
335 * names, and refer to them later using indexes into that array.
336 * We maintain an array of selector values indexed by common clock
337 * index values in order to map between these common clock indexes
338 * and the selector values used by the hardware.
340 * Like dividers, a selector can be modified, but to do so a clock
341 * must be enabled, and a trigger must be used to commit the change.
344 u32 offset; /* selector register offset */
345 u32 shift; /* field shift */
346 u32 width; /* field width */
348 u32 parent_count; /* number of entries in parent_sel[] */
349 u32 *parent_sel; /* array of parent selector values */
350 u8 clk_index; /* current selected index in parent_sel[] */
353 /* Selector initialization macro */
354 #define SELECTOR(_offset, _shift, _width) \
356 .offset = (_offset), \
359 .clk_index = BAD_CLK_INDEX, \
363 * Making changes to a variable divider or a selector for a clock
364 * requires the use of a trigger. A trigger is defined by a single
365 * bit within a register. To signal a change, a 1 is written into
366 * that bit. To determine when the change has been completed, that
367 * trigger bit is polled; the read value will be 1 while the change
368 * is in progress, and 0 when it is complete.
370 * Occasionally a clock will have more than one trigger. In this
371 * case, the "pre-trigger" will be used when changing a clock's
372 * selector and/or its pre-divider.
374 struct bcm_clk_trig {
375 u32 offset; /* trigger register offset */
376 u32 bit; /* trigger bit */
377 u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
382 * EXISTS means this trigger exists
384 #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
386 /* Trigger initialization macro */
387 #define TRIGGER(_offset, _bit) \
389 .offset = (_offset), \
391 .flags = FLAG(TRIG, EXISTS), \
394 struct bus_clk_data {
395 struct bcm_clk_gate gate;
398 struct core_clk_data {
399 struct bcm_clk_gate gate;
402 struct peri_clk_data {
403 struct bcm_clk_gate gate;
404 struct bcm_clk_trig pre_trig;
405 struct bcm_clk_div pre_div;
406 struct bcm_clk_trig trig;
407 struct bcm_clk_div div;
408 struct bcm_clk_sel sel;
409 const char *clocks[]; /* must be last; use CLOCKS() to declare */
411 #define CLOCKS(...) { __VA_ARGS__, NULL, }
412 #define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
420 struct peri_clk_data *data;
426 int num_policy_masks;
427 unsigned long policy_freq_offset;
428 int freq_bit_shift; /* 8 for most CCUs */
429 unsigned long policy_ctl_offset;
430 unsigned long policy0_mask_offset;
431 unsigned long policy1_mask_offset;
432 unsigned long policy2_mask_offset;
433 unsigned long policy3_mask_offset;
434 unsigned long policy0_mask2_offset;
435 unsigned long policy1_mask2_offset;
436 unsigned long policy2_mask2_offset;
437 unsigned long policy3_mask2_offset;
438 unsigned long lvm_en_offset;
441 unsigned long *freq_tbl;
446 struct bus_clk_data *data;
447 unsigned long *freq_tbl;
454 static inline int is_same_clock(struct clk *a, struct clk *b)
459 #define to_clk(p) (&((p)->clk))
460 #define name_to_clk(name) (&((name##_clk).clk))
461 /* declare a struct clk_lookup */
462 #define CLK_LK(name) \
463 {.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
465 static inline struct refclk *to_refclk(struct clk *clock)
467 return container_of(clock, struct refclk, clk);
470 static inline struct peri_clock *to_peri_clk(struct clk *clock)
472 return container_of(clock, struct peri_clock, clk);
475 static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
477 return container_of(clock, struct ccu_clock, clk);
480 static inline struct bus_clock *to_bus_clk(struct clk *clock)
482 return container_of(clock, struct bus_clock, clk);
485 static inline struct ref_clock *to_ref_clk(struct clk *clock)
487 return container_of(clock, struct ref_clock, clk);
490 extern struct clk_ops peri_clk_ops;
491 extern struct clk_ops ccu_clk_ops;
492 extern struct clk_ops bus_clk_ops;
493 extern struct clk_ops ref_clk_ops;
495 extern int clk_get_and_enable(char *clkstr);