1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013 Broadcom Corporation.
6 #include <linux/stddef.h>
8 #ifdef CONFIG_CLK_DEBUG
11 static inline void writel(u32 val, void *addr)
13 printf("Write [0x%p] = 0x%08x\n", addr, val);
17 static inline u32 readl(void *addr)
19 u32 val = *(u32 *)addr;
20 printf("Read [0x%p] = 0x%08x\n", addr, val);
33 extern struct clk_lookup arch_clk_tbl[];
34 extern unsigned int arch_clk_tbl_array_size;
37 * struct clk_ops - standard clock operations
38 * @enable: enable/disable clock, see clk_enable() and clk_disable()
39 * @set_rate: set the clock rate, see clk_set_rate().
40 * @get_rate: get the clock rate, see clk_get_rate().
41 * @round_rate: round a given clock rate, see clk_round_rate().
42 * @set_parent: set the clock's parent, see clk_set_parent().
44 * Group the common clock implementations together so that we
45 * don't have to keep setting the same fiels again. We leave
46 * enable in struct clk.
50 int (*enable) (struct clk *c, int enable);
51 int (*set_rate) (struct clk *c, unsigned long rate);
52 unsigned long (*get_rate) (struct clk *c);
53 unsigned long (*round_rate) (struct clk *c, unsigned long rate);
54 int (*set_parent) (struct clk *c, struct clk *parent);
61 unsigned long rate; /* in HZ */
63 /* programmable divider. 0 means fixed ratio to parent clock */
69 unsigned long ccu_clk_mgr_base;
73 struct refclk *refclk_str_to_clk(const char *name);
75 /* The common clock framework uses u8 to represent a parent index */
76 #define PARENT_COUNT_MAX ((u32)U8_MAX)
78 #define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
79 #define BAD_CLK_NAME ((const char *)-1)
81 #define BAD_SCALED_DIV_VALUE U64_MAX
84 * Utility macros for object flag management. If possible, flags
85 * should be defined such that 0 is the desired default value.
87 #define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
88 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
89 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
90 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
91 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
93 /* Clock field state tests */
95 #define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
96 #define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
97 #define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
98 #define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
99 #define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
100 #define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
102 #define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
104 #define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
105 #define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
106 #define divider_has_fraction(div) (!divider_is_fixed(div) && \
107 (div)->frac_width > 0)
109 #define selector_exists(sel) ((sel)->width != 0)
110 #define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
112 /* Clock type, used to tell common block what it's part of */
114 bcm_clk_none, /* undefined clock type */
121 * Gating control and status is managed by a 32-bit gate register.
123 * There are several types of gating available:
125 * A clock with no gate is assumed to be always enabled.
126 * - hardware-only gating (auto-gating)
127 * Enabling or disabling clocks with this type of gate is
128 * managed automatically by the hardware. Such clocks can be
129 * considered by the software to be enabled. The current status
130 * of auto-gated clocks can be read from the gate status bit.
131 * - software-only gating
132 * Auto-gating is not available for this type of clock.
133 * Instead, software manages whether it's enabled by setting or
134 * clearing the enable bit. The current gate status of a gate
135 * under software control can be read from the gate status bit.
136 * To ensure a change to the gating status is complete, the
137 * status bit can be polled to verify that the gate has entered
139 * - selectable hardware or software gating
140 * Gating for this type of clock can be configured to be either
141 * under software or hardware control. Which type is in use is
142 * determined by the hw_sw_sel bit of the gate register.
144 struct bcm_clk_gate {
145 u32 offset; /* gate register offset */
146 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
147 u32 en_bit; /* 0: disable; 1: enable */
148 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
149 u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
154 * HW means this gate can be auto-gated
155 * SW means the state of this gate can be software controlled
156 * NO_DISABLE means this gate is (only) enabled if under software control
157 * SW_MANAGED means the status of this gate is under software control
158 * ENABLED means this software-managed gate is *supposed* to be enabled
160 #define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
161 #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
162 #define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
163 #define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
164 #define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
165 #define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
168 * Gate initialization macros.
170 * Any gate initially under software control will be enabled.
173 /* A hardware/software gate initially under software control */
174 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
176 .offset = (_offset), \
177 .status_bit = (_status_bit), \
178 .en_bit = (_en_bit), \
179 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
180 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
181 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
182 FLAG(GATE, EXISTS), \
185 /* A hardware/software gate initially under hardware control */
186 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
188 .offset = (_offset), \
189 .status_bit = (_status_bit), \
190 .en_bit = (_en_bit), \
191 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
192 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
193 FLAG(GATE, EXISTS), \
196 /* A hardware-or-enabled gate (enabled if not under hardware control) */
197 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
199 .offset = (_offset), \
200 .status_bit = (_status_bit), \
201 .en_bit = (_en_bit), \
202 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
203 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
204 FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
207 /* A software-only gate */
208 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
210 .offset = (_offset), \
211 .status_bit = (_status_bit), \
212 .en_bit = (_en_bit), \
213 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
214 FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
217 /* A hardware-only gate */
218 #define HW_ONLY_GATE(_offset, _status_bit) \
220 .offset = (_offset), \
221 .status_bit = (_status_bit), \
222 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
226 * Each clock can have zero, one, or two dividers which change the
227 * output rate of the clock. Each divider can be either fixed or
228 * variable. If there are two dividers, they are the "pre-divider"
229 * and the "regular" or "downstream" divider. If there is only one,
230 * there is no pre-divider.
232 * A fixed divider is any non-zero (positive) value, and it
233 * indicates how the input rate is affected by the divider.
235 * The value of a variable divider is maintained in a sub-field of a
236 * 32-bit divider register. The position of the field in the
237 * register is defined by its offset and width. The value recorded
238 * in this field is always 1 less than the value it represents.
240 * In addition, a variable divider can indicate that some subset
241 * of its bits represent a "fractional" part of the divider. Such
242 * bits comprise the low-order portion of the divider field, and can
243 * be viewed as representing the portion of the divider that lies to
244 * the right of the decimal point. Most variable dividers have zero
245 * fractional bits. Variable dividers with non-zero fraction width
246 * still record a value 1 less than the value they represent; the
247 * added 1 does *not* affect the low-order bit in this case, it
248 * affects the bits above the fractional part only. (Often in this
249 * code a divider field value is distinguished from the value it
250 * represents by referring to the latter as a "divisor".)
252 * In order to avoid dealing with fractions, divider arithmetic is
253 * performed using "scaled" values. A scaled value is one that's
254 * been left-shifted by the fractional width of a divider. Dividing
255 * a scaled value by a scaled divisor produces the desired quotient
256 * without loss of precision and without any other special handling
259 * The recorded value of a variable divider can be modified. To
260 * modify either divider (or both), a clock must be enabled (i.e.,
261 * using its gate). In addition, a trigger register (described
262 * below) must be used to commit the change, and polled to verify
263 * the change is complete.
267 struct { /* variable divider */
268 u32 offset; /* divider register offset */
269 u32 shift; /* field shift */
270 u32 width; /* field width */
271 u32 frac_width; /* field fraction width */
273 u64 scaled_div; /* scaled divider value */
275 u32 fixed; /* non-zero fixed divider value */
277 u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
282 * EXISTS means this divider exists
283 * FIXED means it is a fixed-rate divider
285 #define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
286 #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
288 /* Divider initialization macros */
290 /* A fixed (non-zero) divider */
291 #define FIXED_DIVIDER(_value) \
294 .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
297 /* A divider with an integral divisor */
298 #define DIVIDER(_offset, _shift, _width) \
300 .offset = (_offset), \
303 .scaled_div = BAD_SCALED_DIV_VALUE, \
304 .flags = FLAG(DIV, EXISTS), \
307 /* A divider whose divisor has an integer and fractional part */
308 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
310 .offset = (_offset), \
313 .frac_width = (_frac_width), \
314 .scaled_div = BAD_SCALED_DIV_VALUE, \
315 .flags = FLAG(DIV, EXISTS), \
319 * Clocks may have multiple "parent" clocks. If there is more than
320 * one, a selector must be specified to define which of the parent
321 * clocks is currently in use. The selected clock is indicated in a
322 * sub-field of a 32-bit selector register. The range of
323 * representable selector values typically exceeds the number of
324 * available parent clocks. Occasionally the reset value of a
325 * selector field is explicitly set to a (specific) value that does
326 * not correspond to a defined input clock.
328 * We register all known parent clocks with the common clock code
329 * using a packed array (i.e., no empty slots) of (parent) clock
330 * names, and refer to them later using indexes into that array.
331 * We maintain an array of selector values indexed by common clock
332 * index values in order to map between these common clock indexes
333 * and the selector values used by the hardware.
335 * Like dividers, a selector can be modified, but to do so a clock
336 * must be enabled, and a trigger must be used to commit the change.
339 u32 offset; /* selector register offset */
340 u32 shift; /* field shift */
341 u32 width; /* field width */
343 u32 parent_count; /* number of entries in parent_sel[] */
344 u32 *parent_sel; /* array of parent selector values */
345 u8 clk_index; /* current selected index in parent_sel[] */
348 /* Selector initialization macro */
349 #define SELECTOR(_offset, _shift, _width) \
351 .offset = (_offset), \
354 .clk_index = BAD_CLK_INDEX, \
358 * Making changes to a variable divider or a selector for a clock
359 * requires the use of a trigger. A trigger is defined by a single
360 * bit within a register. To signal a change, a 1 is written into
361 * that bit. To determine when the change has been completed, that
362 * trigger bit is polled; the read value will be 1 while the change
363 * is in progress, and 0 when it is complete.
365 * Occasionally a clock will have more than one trigger. In this
366 * case, the "pre-trigger" will be used when changing a clock's
367 * selector and/or its pre-divider.
369 struct bcm_clk_trig {
370 u32 offset; /* trigger register offset */
371 u32 bit; /* trigger bit */
372 u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
377 * EXISTS means this trigger exists
379 #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
381 /* Trigger initialization macro */
382 #define TRIGGER(_offset, _bit) \
384 .offset = (_offset), \
386 .flags = FLAG(TRIG, EXISTS), \
389 struct bus_clk_data {
390 struct bcm_clk_gate gate;
393 struct core_clk_data {
394 struct bcm_clk_gate gate;
397 struct peri_clk_data {
398 struct bcm_clk_gate gate;
399 struct bcm_clk_trig pre_trig;
400 struct bcm_clk_div pre_div;
401 struct bcm_clk_trig trig;
402 struct bcm_clk_div div;
403 struct bcm_clk_sel sel;
404 const char *clocks[]; /* must be last; use CLOCKS() to declare */
406 #define CLOCKS(...) { __VA_ARGS__, NULL, }
407 #define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
415 struct peri_clk_data *data;
421 int num_policy_masks;
422 unsigned long policy_freq_offset;
423 int freq_bit_shift; /* 8 for most CCUs */
424 unsigned long policy_ctl_offset;
425 unsigned long policy0_mask_offset;
426 unsigned long policy1_mask_offset;
427 unsigned long policy2_mask_offset;
428 unsigned long policy3_mask_offset;
429 unsigned long policy0_mask2_offset;
430 unsigned long policy1_mask2_offset;
431 unsigned long policy2_mask2_offset;
432 unsigned long policy3_mask2_offset;
433 unsigned long lvm_en_offset;
436 unsigned long *freq_tbl;
441 struct bus_clk_data *data;
442 unsigned long *freq_tbl;
449 static inline int is_same_clock(struct clk *a, struct clk *b)
454 #define to_clk(p) (&((p)->clk))
455 #define name_to_clk(name) (&((name##_clk).clk))
456 /* declare a struct clk_lookup */
457 #define CLK_LK(name) \
458 {.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
460 static inline struct refclk *to_refclk(struct clk *clock)
462 return container_of(clock, struct refclk, clk);
465 static inline struct peri_clock *to_peri_clk(struct clk *clock)
467 return container_of(clock, struct peri_clock, clk);
470 static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
472 return container_of(clock, struct ccu_clock, clk);
475 static inline struct bus_clock *to_bus_clk(struct clk *clock)
477 return container_of(clock, struct bus_clock, clk);
480 static inline struct ref_clock *to_ref_clk(struct clk *clock)
482 return container_of(clock, struct ref_clock, clk);
485 extern struct clk_ops peri_clk_ops;
486 extern struct clk_ops ccu_clk_ops;
487 extern struct clk_ops bus_clk_ops;
488 extern struct clk_ops ref_clk_ops;
490 extern int clk_get_and_enable(char *clkstr);