3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <linux/types.h>
26 #include <asm/armv7.h>
27 #include <asm/utils.h>
29 #define ARMV7_DCACHE_INVAL_ALL 1
30 #define ARMV7_DCACHE_CLEAN_INVAL_ALL 2
31 #define ARMV7_DCACHE_INVAL_RANGE 3
32 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 4
34 #ifndef CONFIG_SYS_DCACHE_OFF
36 * Write the level and type you want to Cache Size Selection Register(CSSELR)
37 * to get size details from Current Cache Size ID Register(CCSIDR)
39 static void set_csselr(u32 level, u32 type)
40 { u32 csselr = level << 1 | type;
42 /* Write to Cache Size Selection Register(CSSELR) */
43 asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (csselr));
46 static u32 get_ccsidr(void)
50 /* Read current CP15 Cache Size ID Register */
51 asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
55 static u32 get_clidr(void)
59 /* Read current CP15 Cache Level ID Register */
60 asm volatile ("mrc p15,1,%0,c0,c0,1" : "=r" (clidr));
64 static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
65 u32 num_ways, u32 way_shift,
71 * For optimal assembly code:
73 * b. have bigger loop inside
75 for (way = num_ways - 1; way >= 0 ; way--) {
76 for (set = num_sets - 1; set >= 0; set--) {
77 setway = (level << 1) | (set << log2_line_len) |
79 /* Invalidate data/unified cache line by set/way */
80 asm volatile (" mcr p15, 0, %0, c7, c6, 2"
84 /* DSB to make sure the operation is complete */
88 static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
89 u32 num_ways, u32 way_shift,
95 * For optimal assembly code:
97 * b. have bigger loop inside
99 for (way = num_ways - 1; way >= 0 ; way--) {
100 for (set = num_sets - 1; set >= 0; set--) {
101 setway = (level << 1) | (set << log2_line_len) |
104 * Clean & Invalidate data/unified
105 * cache line by set/way
107 asm volatile (" mcr p15, 0, %0, c7, c14, 2"
111 /* DSB to make sure the operation is complete */
115 static void v7_maint_dcache_level_setway(u32 level, u32 operation)
118 u32 num_sets, num_ways, log2_line_len, log2_num_ways;
121 set_csselr(level, ARMV7_CSSELR_IND_DATA_UNIFIED);
123 ccsidr = get_ccsidr();
125 log2_line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
126 CCSIDR_LINE_SIZE_OFFSET) + 2;
127 /* Converting from words to bytes */
130 num_ways = ((ccsidr & CCSIDR_ASSOCIATIVITY_MASK) >>
131 CCSIDR_ASSOCIATIVITY_OFFSET) + 1;
132 num_sets = ((ccsidr & CCSIDR_NUM_SETS_MASK) >>
133 CCSIDR_NUM_SETS_OFFSET) + 1;
135 * According to ARMv7 ARM number of sets and number of ways need
136 * not be a power of 2
138 log2_num_ways = log_2_n_round_up(num_ways);
140 way_shift = (32 - log2_num_ways);
141 if (operation == ARMV7_DCACHE_INVAL_ALL) {
142 v7_inval_dcache_level_setway(level, num_sets, num_ways,
143 way_shift, log2_line_len);
144 } else if (operation == ARMV7_DCACHE_CLEAN_INVAL_ALL) {
145 v7_clean_inval_dcache_level_setway(level, num_sets, num_ways,
146 way_shift, log2_line_len);
150 static void v7_maint_dcache_all(u32 operation)
152 u32 level, cache_type, level_start_bit = 0;
154 u32 clidr = get_clidr();
156 for (level = 0; level < 7; level++) {
157 cache_type = (clidr >> level_start_bit) & 0x7;
158 if ((cache_type == ARMV7_CLIDR_CTYPE_DATA_ONLY) ||
159 (cache_type == ARMV7_CLIDR_CTYPE_INSTRUCTION_DATA) ||
160 (cache_type == ARMV7_CLIDR_CTYPE_UNIFIED))
161 v7_maint_dcache_level_setway(level, operation);
162 level_start_bit += 3;
166 static void v7_dcache_clean_inval_range(u32 start,
167 u32 stop, u32 line_len)
171 /* Align start to cache line boundary */
172 start &= ~(line_len - 1);
173 for (mva = start; mva < stop; mva = mva + line_len) {
174 /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
175 asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
179 static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
184 * If start address is not aligned to cache-line do not
185 * invalidate the first cache-line
187 if (start & (line_len - 1)) {
188 printf("ERROR: %s - start address is not aligned - 0x%08x\n",
190 /* move to next cache line */
191 start = (start + line_len - 1) & ~(line_len - 1);
195 * If stop address is not aligned to cache-line do not
196 * invalidate the last cache-line
198 if (stop & (line_len - 1)) {
199 printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
201 /* align to the beginning of this cache line */
202 stop &= ~(line_len - 1);
205 for (mva = start; mva < stop; mva = mva + line_len) {
206 /* DCIMVAC - Invalidate data cache by MVA to PoC */
207 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
211 static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
213 u32 line_len, ccsidr;
215 ccsidr = get_ccsidr();
216 line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
217 CCSIDR_LINE_SIZE_OFFSET) + 2;
218 /* Converting from words to bytes */
220 /* converting from log2(linelen) to linelen */
221 line_len = 1 << line_len;
224 case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
225 v7_dcache_clean_inval_range(start, stop, line_len);
227 case ARMV7_DCACHE_INVAL_RANGE:
228 v7_dcache_inval_range(start, stop, line_len);
232 /* DSB to make sure the operation is complete */
237 static void v7_inval_tlb(void)
239 /* Invalidate entire unified TLB */
240 asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
241 /* Invalidate entire data TLB */
242 asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
243 /* Invalidate entire instruction TLB */
244 asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
245 /* Full system DSB - make sure that the invalidation is complete */
247 /* Full system ISB - make sure the instruction stream sees it */
251 void invalidate_dcache_all(void)
253 v7_maint_dcache_all(ARMV7_DCACHE_INVAL_ALL);
255 v7_outer_cache_inval_all();
259 * Performs a clean & invalidation of the entire data cache
262 void flush_dcache_all(void)
264 v7_maint_dcache_all(ARMV7_DCACHE_CLEAN_INVAL_ALL);
266 v7_outer_cache_flush_all();
270 * Invalidates range in all levels of D-cache/unified cache used:
271 * Affects the range [start, stop - 1]
273 void invalidate_dcache_range(unsigned long start, unsigned long stop)
276 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
278 v7_outer_cache_inval_range(start, stop);
282 * Flush range(clean & invalidate) from all levels of D-cache/unified
284 * Affects the range [start, stop - 1]
286 void flush_dcache_range(unsigned long start, unsigned long stop)
288 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
290 v7_outer_cache_flush_range(start, stop);
293 void arm_init_before_mmu(void)
295 v7_outer_cache_enable();
296 invalidate_dcache_all();
300 void mmu_page_table_flush(unsigned long start, unsigned long stop)
302 flush_dcache_range(start, stop);
307 * Flush range from all levels of d-cache/unified-cache used:
308 * Affects the range [start, start + size - 1]
310 void flush_cache(unsigned long start, unsigned long size)
312 flush_dcache_range(start, start + size);
314 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
315 void invalidate_dcache_all(void)
319 void flush_dcache_all(void)
323 void invalidate_dcache_range(unsigned long start, unsigned long stop)
327 void flush_dcache_range(unsigned long start, unsigned long stop)
331 void arm_init_before_mmu(void)
335 void flush_cache(unsigned long start, unsigned long size)
339 void mmu_page_table_flush(unsigned long start, unsigned long stop)
343 void arm_init_domains(void)
346 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
348 #ifndef CONFIG_SYS_ICACHE_OFF
349 /* Invalidate entire I-cache and branch predictor array */
350 void invalidate_icache_all(void)
353 * Invalidate all instruction caches to PoU.
354 * Also flushes branch target cache.
356 asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
358 /* Invalidate entire branch predictor array */
359 asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
361 /* Full system DSB - make sure that the invalidation is complete */
364 /* ISB - make sure the instruction stream sees it */
368 void invalidate_icache_all(void)
374 * Stub implementations for outer cache operations
376 void __v7_outer_cache_enable(void)
379 void v7_outer_cache_enable(void)
380 __attribute__((weak, alias("__v7_outer_cache_enable")));
382 void __v7_outer_cache_disable(void)
385 void v7_outer_cache_disable(void)
386 __attribute__((weak, alias("__v7_outer_cache_disable")));
388 void __v7_outer_cache_flush_all(void)
391 void v7_outer_cache_flush_all(void)
392 __attribute__((weak, alias("__v7_outer_cache_flush_all")));
394 void __v7_outer_cache_inval_all(void)
397 void v7_outer_cache_inval_all(void)
398 __attribute__((weak, alias("__v7_outer_cache_inval_all")));
400 void __v7_outer_cache_flush_range(u32 start, u32 end)
403 void v7_outer_cache_flush_range(u32 start, u32 end)
404 __attribute__((weak, alias("__v7_outer_cache_flush_range")));
406 void __v7_outer_cache_inval_range(u32 start, u32 end)
409 void v7_outer_cache_inval_range(u32 start, u32 end)
410 __attribute__((weak, alias("__v7_outer_cache_inval_range")));