3 * Texas Instruments, <www.ti.com>
4 * Aneesh V <aneesh@ti.com>
6 * SPDX-License-Identifier: GPL-2.0+
8 #include <linux/types.h>
10 #include <asm/armv7.h>
11 #include <asm/utils.h>
13 #define ARMV7_DCACHE_INVAL_RANGE 1
14 #define ARMV7_DCACHE_CLEAN_INVAL_RANGE 2
16 #ifndef CONFIG_SYS_DCACHE_OFF
18 /* Asm functions from cache_v7_asm.S */
19 void v7_flush_dcache_all(void);
20 void v7_invalidate_dcache_all(void);
22 static u32 get_ccsidr(void)
26 /* Read current CP15 Cache Size ID Register */
27 asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr));
31 static void v7_dcache_clean_inval_range(u32 start, u32 stop, u32 line_len)
35 /* Align start to cache line boundary */
36 start &= ~(line_len - 1);
37 for (mva = start; mva < stop; mva = mva + line_len) {
38 /* DCCIMVAC - Clean & Invalidate data cache by MVA to PoC */
39 asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva));
43 static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
48 * If start address is not aligned to cache-line do not
49 * invalidate the first cache-line
51 if (start & (line_len - 1)) {
52 printf("ERROR: %s - start address is not aligned - 0x%08x\n",
54 /* move to next cache line */
55 start = (start + line_len - 1) & ~(line_len - 1);
59 * If stop address is not aligned to cache-line do not
60 * invalidate the last cache-line
62 if (stop & (line_len - 1)) {
63 printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
65 /* align to the beginning of this cache line */
66 stop &= ~(line_len - 1);
69 for (mva = start; mva < stop; mva = mva + line_len) {
70 /* DCIMVAC - Invalidate data cache by MVA to PoC */
71 asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva));
75 static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
79 ccsidr = get_ccsidr();
80 line_len = ((ccsidr & CCSIDR_LINE_SIZE_MASK) >>
81 CCSIDR_LINE_SIZE_OFFSET) + 2;
82 /* Converting from words to bytes */
84 /* converting from log2(linelen) to linelen */
85 line_len = 1 << line_len;
88 case ARMV7_DCACHE_CLEAN_INVAL_RANGE:
89 v7_dcache_clean_inval_range(start, stop, line_len);
91 case ARMV7_DCACHE_INVAL_RANGE:
92 v7_dcache_inval_range(start, stop, line_len);
96 /* DSB to make sure the operation is complete */
101 static void v7_inval_tlb(void)
103 /* Invalidate entire unified TLB */
104 asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0));
105 /* Invalidate entire data TLB */
106 asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0));
107 /* Invalidate entire instruction TLB */
108 asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
109 /* Full system DSB - make sure that the invalidation is complete */
111 /* Full system ISB - make sure the instruction stream sees it */
115 void invalidate_dcache_all(void)
117 v7_invalidate_dcache_all();
119 v7_outer_cache_inval_all();
123 * Performs a clean & invalidation of the entire data cache
126 void flush_dcache_all(void)
128 v7_flush_dcache_all();
130 v7_outer_cache_flush_all();
134 * Invalidates range in all levels of D-cache/unified cache used:
135 * Affects the range [start, stop - 1]
137 void invalidate_dcache_range(unsigned long start, unsigned long stop)
139 check_cache_range(start, stop);
141 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);
143 v7_outer_cache_inval_range(start, stop);
147 * Flush range(clean & invalidate) from all levels of D-cache/unified
149 * Affects the range [start, stop - 1]
151 void flush_dcache_range(unsigned long start, unsigned long stop)
153 check_cache_range(start, stop);
155 v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);
157 v7_outer_cache_flush_range(start, stop);
160 void arm_init_before_mmu(void)
162 v7_outer_cache_enable();
163 invalidate_dcache_all();
167 void mmu_page_table_flush(unsigned long start, unsigned long stop)
169 flush_dcache_range(start, stop);
172 #else /* #ifndef CONFIG_SYS_DCACHE_OFF */
173 void invalidate_dcache_all(void)
177 void flush_dcache_all(void)
181 void invalidate_dcache_range(unsigned long start, unsigned long stop)
185 void flush_dcache_range(unsigned long start, unsigned long stop)
189 void arm_init_before_mmu(void)
193 void mmu_page_table_flush(unsigned long start, unsigned long stop)
197 void arm_init_domains(void)
200 #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
202 #ifndef CONFIG_SYS_ICACHE_OFF
203 /* Invalidate entire I-cache and branch predictor array */
204 void invalidate_icache_all(void)
207 * Invalidate all instruction caches to PoU.
208 * Also flushes branch target cache.
210 asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
212 /* Invalidate entire branch predictor array */
213 asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
215 /* Full system DSB - make sure that the invalidation is complete */
218 /* ISB - make sure the instruction stream sees it */
222 void invalidate_icache_all(void)
227 /* Stub implementations for outer cache operations */
228 __weak void v7_outer_cache_enable(void) {}
229 __weak void v7_outer_cache_disable(void) {}
230 __weak void v7_outer_cache_flush_all(void) {}
231 __weak void v7_outer_cache_inval_all(void) {}
232 __weak void v7_outer_cache_flush_range(u32 start, u32 end) {}
233 __weak void v7_outer_cache_inval_range(u32 start, u32 end) {}