2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
29 /* exynos4: return pll clock frequency */
30 static unsigned long exynos4_get_pll_clk(int pllreg)
32 struct exynos4_clock *clk =
33 (struct exynos4_clock *)samsung_get_base_clock();
34 unsigned long r, m, p, s, k = 0, mask, fout;
39 r = readl(&clk->apll_con0);
42 r = readl(&clk->mpll_con0);
45 r = readl(&clk->epll_con0);
46 k = readl(&clk->epll_con1);
49 r = readl(&clk->vpll_con0);
50 k = readl(&clk->vpll_con1);
53 printf("Unsupported PLL (%d)\n", pllreg);
58 * APLL_CON: MIDV [25:16]
59 * MPLL_CON: MIDV [25:16]
60 * EPLL_CON: MIDV [24:16]
61 * VPLL_CON: MIDV [24:16]
63 if (pllreg == APLL || pllreg == MPLL)
75 freq = CONFIG_SYS_CLK_FREQ;
79 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
80 fout = (m + k / 65536) * (freq / (p * (1 << s)));
81 } else if (pllreg == VPLL) {
83 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
84 fout = (m + k / 1024) * (freq / (p * (1 << s)));
88 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
89 fout = m * (freq / (p * (1 << (s - 1))));
95 /* exynos5: return pll clock frequency */
96 static unsigned long exynos5_get_pll_clk(int pllreg)
98 struct exynos5_clock *clk =
99 (struct exynos5_clock *)samsung_get_base_clock();
100 unsigned long r, m, p, s, k = 0, mask, fout;
101 unsigned int freq, pll_div2_sel, fout_sel;
105 r = readl(&clk->apll_con0);
108 r = readl(&clk->mpll_con0);
111 r = readl(&clk->epll_con0);
112 k = readl(&clk->epll_con1);
115 r = readl(&clk->vpll_con0);
116 k = readl(&clk->vpll_con1);
119 r = readl(&clk->bpll_con0);
122 printf("Unsupported PLL (%d)\n", pllreg);
127 * APLL_CON: MIDV [25:16]
128 * MPLL_CON: MIDV [25:16]
129 * EPLL_CON: MIDV [24:16]
130 * VPLL_CON: MIDV [24:16]
131 * BPLL_CON: MIDV [25:16]
133 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
138 m = (r >> 16) & mask;
145 freq = CONFIG_SYS_CLK_FREQ;
147 if (pllreg == EPLL) {
149 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
150 fout = (m + k / 65536) * (freq / (p * (1 << s)));
151 } else if (pllreg == VPLL) {
153 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
154 fout = (m + k / 1024) * (freq / (p * (1 << s)));
158 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
159 fout = m * (freq / (p * (1 << (s - 1))));
162 /* According to the user manual, in EVT1 MPLL and BPLL always gives
163 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
164 if (pllreg == MPLL || pllreg == BPLL) {
165 pll_div2_sel = readl(&clk->pll_div2_sel);
169 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
170 & MPLL_FOUT_SEL_MASK;
173 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
174 & BPLL_FOUT_SEL_MASK;
188 /* exynos4: return ARM clock frequency */
189 static unsigned long exynos4_get_arm_clk(void)
191 struct exynos4_clock *clk =
192 (struct exynos4_clock *)samsung_get_base_clock();
194 unsigned long armclk;
195 unsigned int core_ratio;
196 unsigned int core2_ratio;
198 div = readl(&clk->div_cpu0);
200 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
201 core_ratio = (div >> 0) & 0x7;
202 core2_ratio = (div >> 28) & 0x7;
204 armclk = get_pll_clk(APLL) / (core_ratio + 1);
205 armclk /= (core2_ratio + 1);
210 /* exynos5: return ARM clock frequency */
211 static unsigned long exynos5_get_arm_clk(void)
213 struct exynos5_clock *clk =
214 (struct exynos5_clock *)samsung_get_base_clock();
216 unsigned long armclk;
217 unsigned int arm_ratio;
218 unsigned int arm2_ratio;
220 div = readl(&clk->div_cpu0);
222 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
223 arm_ratio = (div >> 0) & 0x7;
224 arm2_ratio = (div >> 28) & 0x7;
226 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
227 armclk /= (arm2_ratio + 1);
232 /* exynos4: return pwm clock frequency */
233 static unsigned long exynos4_get_pwm_clk(void)
235 struct exynos4_clock *clk =
236 (struct exynos4_clock *)samsung_get_base_clock();
237 unsigned long pclk, sclk;
241 if (s5p_get_cpu_rev() == 0) {
246 sel = readl(&clk->src_peril0);
247 sel = (sel >> 24) & 0xf;
250 sclk = get_pll_clk(MPLL);
252 sclk = get_pll_clk(EPLL);
254 sclk = get_pll_clk(VPLL);
262 ratio = readl(&clk->div_peril3);
264 } else if (s5p_get_cpu_rev() == 1) {
265 sclk = get_pll_clk(MPLL);
270 pclk = sclk / (ratio + 1);
275 /* exynos5: return pwm clock frequency */
276 static unsigned long exynos5_get_pwm_clk(void)
278 struct exynos5_clock *clk =
279 (struct exynos5_clock *)samsung_get_base_clock();
280 unsigned long pclk, sclk;
287 ratio = readl(&clk->div_peric3);
289 sclk = get_pll_clk(MPLL);
291 pclk = sclk / (ratio + 1);
296 /* exynos4: return uart clock frequency */
297 static unsigned long exynos4_get_uart_clk(int dev_index)
299 struct exynos4_clock *clk =
300 (struct exynos4_clock *)samsung_get_base_clock();
301 unsigned long uclk, sclk;
314 sel = readl(&clk->src_peril0);
315 sel = (sel >> (dev_index << 2)) & 0xf;
318 sclk = get_pll_clk(MPLL);
320 sclk = get_pll_clk(EPLL);
322 sclk = get_pll_clk(VPLL);
331 * UART3_RATIO [12:15]
332 * UART4_RATIO [16:19]
333 * UART5_RATIO [23:20]
335 ratio = readl(&clk->div_peril0);
336 ratio = (ratio >> (dev_index << 2)) & 0xf;
338 uclk = sclk / (ratio + 1);
343 /* exynos5: return uart clock frequency */
344 static unsigned long exynos5_get_uart_clk(int dev_index)
346 struct exynos5_clock *clk =
347 (struct exynos5_clock *)samsung_get_base_clock();
348 unsigned long uclk, sclk;
361 sel = readl(&clk->src_peric0);
362 sel = (sel >> (dev_index << 2)) & 0xf;
365 sclk = get_pll_clk(MPLL);
367 sclk = get_pll_clk(EPLL);
369 sclk = get_pll_clk(VPLL);
378 * UART3_RATIO [12:15]
379 * UART4_RATIO [16:19]
380 * UART5_RATIO [23:20]
382 ratio = readl(&clk->div_peric0);
383 ratio = (ratio >> (dev_index << 2)) & 0xf;
385 uclk = sclk / (ratio + 1);
390 /* exynos4: set the mmc clock */
391 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
393 struct exynos4_clock *clk =
394 (struct exynos4_clock *)samsung_get_base_clock();
400 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
402 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
405 addr = (unsigned int)&clk->div_fsys1;
407 addr = (unsigned int)&clk->div_fsys2;
412 val &= ~(0xff << ((dev_index << 4) + 8));
413 val |= (div & 0xff) << ((dev_index << 4) + 8);
417 /* exynos5: set the mmc clock */
418 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
420 struct exynos5_clock *clk =
421 (struct exynos5_clock *)samsung_get_base_clock();
427 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
429 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
432 addr = (unsigned int)&clk->div_fsys1;
434 addr = (unsigned int)&clk->div_fsys2;
439 val &= ~(0xff << ((dev_index << 4) + 8));
440 val |= (div & 0xff) << ((dev_index << 4) + 8);
444 /* get_lcd_clk: return lcd clock frequency */
445 static unsigned long exynos4_get_lcd_clk(void)
447 struct exynos4_clock *clk =
448 (struct exynos4_clock *)samsung_get_base_clock();
449 unsigned long pclk, sclk;
457 sel = readl(&clk->src_lcd0);
466 sclk = get_pll_clk(MPLL);
468 sclk = get_pll_clk(EPLL);
470 sclk = get_pll_clk(VPLL);
478 ratio = readl(&clk->div_lcd0);
481 pclk = sclk / (ratio + 1);
486 /* get_lcd_clk: return lcd clock frequency */
487 static unsigned long exynos5_get_lcd_clk(void)
489 struct exynos5_clock *clk =
490 (struct exynos5_clock *)samsung_get_base_clock();
491 unsigned long pclk, sclk;
499 sel = readl(&clk->src_disp1_0);
508 sclk = get_pll_clk(MPLL);
510 sclk = get_pll_clk(EPLL);
512 sclk = get_pll_clk(VPLL);
520 ratio = readl(&clk->div_disp1_0);
523 pclk = sclk / (ratio + 1);
528 void exynos4_set_lcd_clk(void)
530 struct exynos4_clock *clk =
531 (struct exynos4_clock *)samsung_get_base_clock();
532 unsigned int cfg = 0;
544 cfg = readl(&clk->gate_block);
546 writel(cfg, &clk->gate_block);
552 * MDNIE_PWM0_SEL [8:11]
554 * set lcd0 src clock 0x6: SCLK_MPLL
556 cfg = readl(&clk->src_lcd0);
559 writel(cfg, &clk->src_lcd0);
569 * Gating all clocks for FIMD0
571 cfg = readl(&clk->gate_ip_lcd0);
573 writel(cfg, &clk->gate_ip_lcd0);
579 * MDNIE_PWM0_RATIO [11:8]
580 * MDNIE_PWM_PRE_RATIO [15:12]
581 * MIPI0_RATIO [19:16]
582 * MIPI0_PRE_RATIO [23:20]
587 writel(cfg, &clk->div_lcd0);
590 void exynos5_set_lcd_clk(void)
592 struct exynos5_clock *clk =
593 (struct exynos5_clock *)samsung_get_base_clock();
594 unsigned int cfg = 0;
606 cfg = readl(&clk->gate_block);
608 writel(cfg, &clk->gate_block);
614 * MDNIE_PWM0_SEL [8:11]
616 * set lcd0 src clock 0x6: SCLK_MPLL
618 cfg = readl(&clk->src_disp1_0);
621 writel(cfg, &clk->src_disp1_0);
631 * Gating all clocks for FIMD0
633 cfg = readl(&clk->gate_ip_disp1);
635 writel(cfg, &clk->gate_ip_disp1);
641 * MDNIE_PWM0_RATIO [11:8]
642 * MDNIE_PWM_PRE_RATIO [15:12]
643 * MIPI0_RATIO [19:16]
644 * MIPI0_PRE_RATIO [23:20]
649 writel(cfg, &clk->div_disp1_0);
652 void exynos4_set_mipi_clk(void)
654 struct exynos4_clock *clk =
655 (struct exynos4_clock *)samsung_get_base_clock();
656 unsigned int cfg = 0;
662 * MDNIE_PWM0_SEL [8:11]
664 * set mipi0 src clock 0x6: SCLK_MPLL
666 cfg = readl(&clk->src_lcd0);
669 writel(cfg, &clk->src_lcd0);
675 * MDNIE_PWM0_MASK [8]
677 * set src mask mipi0 0x1: Unmask
679 cfg = readl(&clk->src_mask_lcd0);
681 writel(cfg, &clk->src_mask_lcd0);
691 * Gating all clocks for MIPI0
693 cfg = readl(&clk->gate_ip_lcd0);
695 writel(cfg, &clk->gate_ip_lcd0);
701 * MDNIE_PWM0_RATIO [11:8]
702 * MDNIE_PWM_PRE_RATIO [15:12]
703 * MIPI0_RATIO [19:16]
704 * MIPI0_PRE_RATIO [23:20]
709 writel(cfg, &clk->div_lcd0);
715 * exynos5: obtaining the I2C clock
717 static unsigned long exynos5_get_i2c_clk(void)
719 struct exynos5_clock *clk =
720 (struct exynos5_clock *)samsung_get_base_clock();
721 unsigned long aclk_66, aclk_66_pre, sclk;
724 sclk = get_pll_clk(MPLL);
726 ratio = (readl(&clk->div_top1)) >> 24;
728 aclk_66_pre = sclk / (ratio + 1);
729 ratio = readl(&clk->div_top0);
731 aclk_66 = aclk_66_pre / (ratio + 1);
735 unsigned long get_pll_clk(int pllreg)
737 if (cpu_is_exynos5())
738 return exynos5_get_pll_clk(pllreg);
740 return exynos4_get_pll_clk(pllreg);
743 unsigned long get_arm_clk(void)
745 if (cpu_is_exynos5())
746 return exynos5_get_arm_clk();
748 return exynos4_get_arm_clk();
751 unsigned long get_i2c_clk(void)
753 if (cpu_is_exynos5()) {
754 return exynos5_get_i2c_clk();
756 debug("I2C clock is not set for this CPU\n");
761 unsigned long get_pwm_clk(void)
763 if (cpu_is_exynos5())
764 return exynos5_get_pwm_clk();
766 return exynos4_get_pwm_clk();
769 unsigned long get_uart_clk(int dev_index)
771 if (cpu_is_exynos5())
772 return exynos5_get_uart_clk(dev_index);
774 return exynos4_get_uart_clk(dev_index);
777 void set_mmc_clk(int dev_index, unsigned int div)
779 if (cpu_is_exynos5())
780 exynos5_set_mmc_clk(dev_index, div);
782 exynos4_set_mmc_clk(dev_index, div);
785 unsigned long get_lcd_clk(void)
787 if (cpu_is_exynos4())
788 return exynos4_get_lcd_clk();
790 return exynos5_get_lcd_clk();
793 void set_lcd_clk(void)
795 if (cpu_is_exynos4())
796 exynos4_set_lcd_clk();
798 exynos5_set_lcd_clk();
801 void set_mipi_clk(void)
803 if (cpu_is_exynos4())
804 exynos4_set_mipi_clk();