2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/periph.h>
30 /* Epll Clock division values to achive different frequency output */
31 static struct set_epll_con_val exynos5_epll_div[] = {
32 { 192000000, 0, 48, 3, 1, 0 },
33 { 180000000, 0, 45, 3, 1, 0 },
34 { 73728000, 1, 73, 3, 3, 47710 },
35 { 67737600, 1, 90, 4, 3, 20762 },
36 { 49152000, 0, 49, 3, 3, 9961 },
37 { 45158400, 0, 45, 3, 3, 10381 },
38 { 180633600, 0, 45, 3, 1, 10381 }
41 /* exynos: return pll clock frequency */
42 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
44 unsigned long m, p, s = 0, mask, fout;
47 * APLL_CON: MIDV [25:16]
48 * MPLL_CON: MIDV [25:16]
49 * EPLL_CON: MIDV [24:16]
50 * VPLL_CON: MIDV [24:16]
51 * BPLL_CON: MIDV [25:16]: Exynos5
53 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
65 freq = CONFIG_SYS_CLK_FREQ;
69 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
70 fout = (m + k / 65536) * (freq / (p * (1 << s)));
71 } else if (pllreg == VPLL) {
73 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
74 fout = (m + k / 1024) * (freq / (p * (1 << s)));
78 /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
79 fout = m * (freq / (p * (1 << (s - 1))));
85 /* exynos4: return pll clock frequency */
86 static unsigned long exynos4_get_pll_clk(int pllreg)
88 struct exynos4_clock *clk =
89 (struct exynos4_clock *)samsung_get_base_clock();
90 unsigned long r, k = 0;
94 r = readl(&clk->apll_con0);
97 r = readl(&clk->mpll_con0);
100 r = readl(&clk->epll_con0);
101 k = readl(&clk->epll_con1);
104 r = readl(&clk->vpll_con0);
105 k = readl(&clk->vpll_con1);
108 printf("Unsupported PLL (%d)\n", pllreg);
112 return exynos_get_pll_clk(pllreg, r, k);
115 /* exynos4x12: return pll clock frequency */
116 static unsigned long exynos4x12_get_pll_clk(int pllreg)
118 struct exynos4x12_clock *clk =
119 (struct exynos4x12_clock *)samsung_get_base_clock();
120 unsigned long r, k = 0;
124 r = readl(&clk->apll_con0);
127 r = readl(&clk->mpll_con0);
130 r = readl(&clk->epll_con0);
131 k = readl(&clk->epll_con1);
134 r = readl(&clk->vpll_con0);
135 k = readl(&clk->vpll_con1);
138 printf("Unsupported PLL (%d)\n", pllreg);
142 return exynos_get_pll_clk(pllreg, r, k);
145 /* exynos5: return pll clock frequency */
146 static unsigned long exynos5_get_pll_clk(int pllreg)
148 struct exynos5_clock *clk =
149 (struct exynos5_clock *)samsung_get_base_clock();
150 unsigned long r, k = 0, fout;
151 unsigned int pll_div2_sel, fout_sel;
155 r = readl(&clk->apll_con0);
158 r = readl(&clk->mpll_con0);
161 r = readl(&clk->epll_con0);
162 k = readl(&clk->epll_con1);
165 r = readl(&clk->vpll_con0);
166 k = readl(&clk->vpll_con1);
169 r = readl(&clk->bpll_con0);
172 printf("Unsupported PLL (%d)\n", pllreg);
176 fout = exynos_get_pll_clk(pllreg, r, k);
178 /* According to the user manual, in EVT1 MPLL and BPLL always gives
179 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
180 if (pllreg == MPLL || pllreg == BPLL) {
181 pll_div2_sel = readl(&clk->pll_div2_sel);
185 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
186 & MPLL_FOUT_SEL_MASK;
189 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
190 & BPLL_FOUT_SEL_MASK;
204 /* exynos4: return ARM clock frequency */
205 static unsigned long exynos4_get_arm_clk(void)
207 struct exynos4_clock *clk =
208 (struct exynos4_clock *)samsung_get_base_clock();
210 unsigned long armclk;
211 unsigned int core_ratio;
212 unsigned int core2_ratio;
214 div = readl(&clk->div_cpu0);
216 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
217 core_ratio = (div >> 0) & 0x7;
218 core2_ratio = (div >> 28) & 0x7;
220 armclk = get_pll_clk(APLL) / (core_ratio + 1);
221 armclk /= (core2_ratio + 1);
226 /* exynos4x12: return ARM clock frequency */
227 static unsigned long exynos4x12_get_arm_clk(void)
229 struct exynos4x12_clock *clk =
230 (struct exynos4x12_clock *)samsung_get_base_clock();
232 unsigned long armclk;
233 unsigned int core_ratio;
234 unsigned int core2_ratio;
236 div = readl(&clk->div_cpu0);
238 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
239 core_ratio = (div >> 0) & 0x7;
240 core2_ratio = (div >> 28) & 0x7;
242 armclk = get_pll_clk(APLL) / (core_ratio + 1);
243 armclk /= (core2_ratio + 1);
248 /* exynos5: return ARM clock frequency */
249 static unsigned long exynos5_get_arm_clk(void)
251 struct exynos5_clock *clk =
252 (struct exynos5_clock *)samsung_get_base_clock();
254 unsigned long armclk;
255 unsigned int arm_ratio;
256 unsigned int arm2_ratio;
258 div = readl(&clk->div_cpu0);
260 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
261 arm_ratio = (div >> 0) & 0x7;
262 arm2_ratio = (div >> 28) & 0x7;
264 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
265 armclk /= (arm2_ratio + 1);
270 /* exynos4: return pwm clock frequency */
271 static unsigned long exynos4_get_pwm_clk(void)
273 struct exynos4_clock *clk =
274 (struct exynos4_clock *)samsung_get_base_clock();
275 unsigned long pclk, sclk;
279 if (s5p_get_cpu_rev() == 0) {
284 sel = readl(&clk->src_peril0);
285 sel = (sel >> 24) & 0xf;
288 sclk = get_pll_clk(MPLL);
290 sclk = get_pll_clk(EPLL);
292 sclk = get_pll_clk(VPLL);
300 ratio = readl(&clk->div_peril3);
302 } else if (s5p_get_cpu_rev() == 1) {
303 sclk = get_pll_clk(MPLL);
308 pclk = sclk / (ratio + 1);
313 /* exynos4x12: return pwm clock frequency */
314 static unsigned long exynos4x12_get_pwm_clk(void)
316 unsigned long pclk, sclk;
319 sclk = get_pll_clk(MPLL);
322 pclk = sclk / (ratio + 1);
327 /* exynos5: return pwm clock frequency */
328 static unsigned long exynos5_get_pwm_clk(void)
330 struct exynos5_clock *clk =
331 (struct exynos5_clock *)samsung_get_base_clock();
332 unsigned long pclk, sclk;
339 ratio = readl(&clk->div_peric3);
341 sclk = get_pll_clk(MPLL);
343 pclk = sclk / (ratio + 1);
348 /* exynos4: return uart clock frequency */
349 static unsigned long exynos4_get_uart_clk(int dev_index)
351 struct exynos4_clock *clk =
352 (struct exynos4_clock *)samsung_get_base_clock();
353 unsigned long uclk, sclk;
366 sel = readl(&clk->src_peril0);
367 sel = (sel >> (dev_index << 2)) & 0xf;
370 sclk = get_pll_clk(MPLL);
372 sclk = get_pll_clk(EPLL);
374 sclk = get_pll_clk(VPLL);
383 * UART3_RATIO [12:15]
384 * UART4_RATIO [16:19]
385 * UART5_RATIO [23:20]
387 ratio = readl(&clk->div_peril0);
388 ratio = (ratio >> (dev_index << 2)) & 0xf;
390 uclk = sclk / (ratio + 1);
395 /* exynos4x12: return uart clock frequency */
396 static unsigned long exynos4x12_get_uart_clk(int dev_index)
398 struct exynos4x12_clock *clk =
399 (struct exynos4x12_clock *)samsung_get_base_clock();
400 unsigned long uclk, sclk;
412 sel = readl(&clk->src_peril0);
413 sel = (sel >> (dev_index << 2)) & 0xf;
416 sclk = get_pll_clk(MPLL);
418 sclk = get_pll_clk(EPLL);
420 sclk = get_pll_clk(VPLL);
429 * UART3_RATIO [12:15]
430 * UART4_RATIO [16:19]
432 ratio = readl(&clk->div_peril0);
433 ratio = (ratio >> (dev_index << 2)) & 0xf;
435 uclk = sclk / (ratio + 1);
440 /* exynos5: return uart clock frequency */
441 static unsigned long exynos5_get_uart_clk(int dev_index)
443 struct exynos5_clock *clk =
444 (struct exynos5_clock *)samsung_get_base_clock();
445 unsigned long uclk, sclk;
458 sel = readl(&clk->src_peric0);
459 sel = (sel >> (dev_index << 2)) & 0xf;
462 sclk = get_pll_clk(MPLL);
464 sclk = get_pll_clk(EPLL);
466 sclk = get_pll_clk(VPLL);
475 * UART3_RATIO [12:15]
476 * UART4_RATIO [16:19]
477 * UART5_RATIO [23:20]
479 ratio = readl(&clk->div_peric0);
480 ratio = (ratio >> (dev_index << 2)) & 0xf;
482 uclk = sclk / (ratio + 1);
487 /* exynos4: set the mmc clock */
488 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
490 struct exynos4_clock *clk =
491 (struct exynos4_clock *)samsung_get_base_clock();
497 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
499 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
502 addr = (unsigned int)&clk->div_fsys1;
504 addr = (unsigned int)&clk->div_fsys2;
509 val &= ~(0xff << ((dev_index << 4) + 8));
510 val |= (div & 0xff) << ((dev_index << 4) + 8);
514 /* exynos4x12: set the mmc clock */
515 static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
517 struct exynos4x12_clock *clk =
518 (struct exynos4x12_clock *)samsung_get_base_clock();
524 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
526 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
529 addr = (unsigned int)&clk->div_fsys1;
531 addr = (unsigned int)&clk->div_fsys2;
536 val &= ~(0xff << ((dev_index << 4) + 8));
537 val |= (div & 0xff) << ((dev_index << 4) + 8);
541 /* exynos5: set the mmc clock */
542 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
544 struct exynos5_clock *clk =
545 (struct exynos5_clock *)samsung_get_base_clock();
551 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
553 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
556 addr = (unsigned int)&clk->div_fsys1;
558 addr = (unsigned int)&clk->div_fsys2;
563 val &= ~(0xff << ((dev_index << 4) + 8));
564 val |= (div & 0xff) << ((dev_index << 4) + 8);
568 /* get_lcd_clk: return lcd clock frequency */
569 static unsigned long exynos4_get_lcd_clk(void)
571 struct exynos4_clock *clk =
572 (struct exynos4_clock *)samsung_get_base_clock();
573 unsigned long pclk, sclk;
581 sel = readl(&clk->src_lcd0);
590 sclk = get_pll_clk(MPLL);
592 sclk = get_pll_clk(EPLL);
594 sclk = get_pll_clk(VPLL);
602 ratio = readl(&clk->div_lcd0);
605 pclk = sclk / (ratio + 1);
610 /* get_lcd_clk: return lcd clock frequency */
611 static unsigned long exynos5_get_lcd_clk(void)
613 struct exynos5_clock *clk =
614 (struct exynos5_clock *)samsung_get_base_clock();
615 unsigned long pclk, sclk;
623 sel = readl(&clk->src_disp1_0);
632 sclk = get_pll_clk(MPLL);
634 sclk = get_pll_clk(EPLL);
636 sclk = get_pll_clk(VPLL);
644 ratio = readl(&clk->div_disp1_0);
647 pclk = sclk / (ratio + 1);
652 void exynos4_set_lcd_clk(void)
654 struct exynos4_clock *clk =
655 (struct exynos4_clock *)samsung_get_base_clock();
656 unsigned int cfg = 0;
668 cfg = readl(&clk->gate_block);
670 writel(cfg, &clk->gate_block);
676 * MDNIE_PWM0_SEL [8:11]
678 * set lcd0 src clock 0x6: SCLK_MPLL
680 cfg = readl(&clk->src_lcd0);
683 writel(cfg, &clk->src_lcd0);
693 * Gating all clocks for FIMD0
695 cfg = readl(&clk->gate_ip_lcd0);
697 writel(cfg, &clk->gate_ip_lcd0);
703 * MDNIE_PWM0_RATIO [11:8]
704 * MDNIE_PWM_PRE_RATIO [15:12]
705 * MIPI0_RATIO [19:16]
706 * MIPI0_PRE_RATIO [23:20]
711 writel(cfg, &clk->div_lcd0);
714 void exynos5_set_lcd_clk(void)
716 struct exynos5_clock *clk =
717 (struct exynos5_clock *)samsung_get_base_clock();
718 unsigned int cfg = 0;
730 cfg = readl(&clk->gate_block);
732 writel(cfg, &clk->gate_block);
738 * MDNIE_PWM0_SEL [8:11]
740 * set lcd0 src clock 0x6: SCLK_MPLL
742 cfg = readl(&clk->src_disp1_0);
745 writel(cfg, &clk->src_disp1_0);
755 * Gating all clocks for FIMD0
757 cfg = readl(&clk->gate_ip_disp1);
759 writel(cfg, &clk->gate_ip_disp1);
765 * MDNIE_PWM0_RATIO [11:8]
766 * MDNIE_PWM_PRE_RATIO [15:12]
767 * MIPI0_RATIO [19:16]
768 * MIPI0_PRE_RATIO [23:20]
773 writel(cfg, &clk->div_disp1_0);
776 void exynos4_set_mipi_clk(void)
778 struct exynos4_clock *clk =
779 (struct exynos4_clock *)samsung_get_base_clock();
780 unsigned int cfg = 0;
786 * MDNIE_PWM0_SEL [8:11]
788 * set mipi0 src clock 0x6: SCLK_MPLL
790 cfg = readl(&clk->src_lcd0);
793 writel(cfg, &clk->src_lcd0);
799 * MDNIE_PWM0_MASK [8]
801 * set src mask mipi0 0x1: Unmask
803 cfg = readl(&clk->src_mask_lcd0);
805 writel(cfg, &clk->src_mask_lcd0);
815 * Gating all clocks for MIPI0
817 cfg = readl(&clk->gate_ip_lcd0);
819 writel(cfg, &clk->gate_ip_lcd0);
825 * MDNIE_PWM0_RATIO [11:8]
826 * MDNIE_PWM_PRE_RATIO [15:12]
827 * MIPI0_RATIO [19:16]
828 * MIPI0_PRE_RATIO [23:20]
833 writel(cfg, &clk->div_lcd0);
839 * exynos5: obtaining the I2C clock
841 static unsigned long exynos5_get_i2c_clk(void)
843 struct exynos5_clock *clk =
844 (struct exynos5_clock *)samsung_get_base_clock();
845 unsigned long aclk_66, aclk_66_pre, sclk;
848 sclk = get_pll_clk(MPLL);
850 ratio = (readl(&clk->div_top1)) >> 24;
852 aclk_66_pre = sclk / (ratio + 1);
853 ratio = readl(&clk->div_top0);
855 aclk_66 = aclk_66_pre / (ratio + 1);
859 int exynos5_set_epll_clk(unsigned long rate)
861 unsigned int epll_con, epll_con_k;
863 unsigned int lockcnt;
865 struct exynos5_clock *clk =
866 (struct exynos5_clock *)samsung_get_base_clock();
868 epll_con = readl(&clk->epll_con0);
869 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
870 EPLL_CON0_LOCK_DET_EN_SHIFT) |
871 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
872 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
873 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
875 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
876 if (exynos5_epll_div[i].freq_out == rate)
880 if (i == ARRAY_SIZE(exynos5_epll_div))
883 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
884 epll_con |= exynos5_epll_div[i].en_lock_det <<
885 EPLL_CON0_LOCK_DET_EN_SHIFT;
886 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
887 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
888 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
891 * Required period ( in cycles) to genarate a stable clock output.
892 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
893 * frequency input (as per spec)
895 lockcnt = 3000 * exynos5_epll_div[i].p_div;
897 writel(lockcnt, &clk->epll_lock);
898 writel(epll_con, &clk->epll_con0);
899 writel(epll_con_k, &clk->epll_con1);
901 start = get_timer(0);
903 while (!(readl(&clk->epll_con0) &
904 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
905 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
906 debug("%s: Timeout waiting for EPLL lock\n", __func__);
913 void exynos5_set_i2s_clk_source(void)
915 struct exynos5_clock *clk =
916 (struct exynos5_clock *)samsung_get_base_clock();
918 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
919 (CLK_SRC_SCLK_EPLL));
922 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
923 unsigned int dst_frq)
925 struct exynos5_clock *clk =
926 (struct exynos5_clock *)samsung_get_base_clock();
929 if ((dst_frq == 0) || (src_frq == 0)) {
930 debug("%s: Invalid requency input for prescaler\n", __func__);
931 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
935 div = (src_frq / dst_frq);
936 if (div > AUDIO_1_RATIO_MASK) {
937 debug("%s: Frequency ratio is out of range\n", __func__);
938 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
941 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
942 (div & AUDIO_1_RATIO_MASK));
947 * Linearly searches for the most accurate main and fine stage clock scalars
948 * (divisors) for a specified target frequency and scalar bit sizes by checking
949 * all multiples of main_scalar_bits values. Will always return scalars up to or
950 * slower than target.
952 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
953 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
954 * @param input_freq Clock frequency to be scaled in Hz
955 * @param target_freq Desired clock frequency in Hz
956 * @param best_fine_scalar Pointer to store the fine stage divisor
958 * @return best_main_scalar Main scalar for desired frequency or -1 if none
961 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
962 unsigned int fine_scalar_bits, unsigned int input_rate,
963 unsigned int target_rate, unsigned int *best_fine_scalar)
966 int best_main_scalar = -1;
967 unsigned int best_error = target_rate;
968 const unsigned int cap = (1 << fine_scalar_bits) - 1;
969 const unsigned int loops = 1 << main_scaler_bits;
971 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
974 assert(best_fine_scalar != NULL);
975 assert(main_scaler_bits <= fine_scalar_bits);
977 *best_fine_scalar = 1;
979 if (input_rate == 0 || target_rate == 0)
982 if (target_rate >= input_rate)
985 for (i = 1; i <= loops; i++) {
986 const unsigned int effective_div = max(min(input_rate / i /
987 target_rate, cap), 1);
988 const unsigned int effective_rate = input_rate / i /
990 const int error = target_rate - effective_rate;
992 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
993 effective_rate, error);
995 if (error >= 0 && error <= best_error) {
997 best_main_scalar = i;
998 *best_fine_scalar = effective_div;
1002 return best_main_scalar;
1005 static int exynos5_set_spi_clk(enum periph_id periph_id,
1008 struct exynos5_clock *clk =
1009 (struct exynos5_clock *)samsung_get_base_clock();
1012 unsigned shift, pre_shift;
1013 unsigned mask = 0xff;
1016 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1018 debug("%s: Cannot set clock rate for periph %d",
1019 __func__, periph_id);
1025 switch (periph_id) {
1026 case PERIPH_ID_SPI0:
1027 reg = &clk->div_peric1;
1031 case PERIPH_ID_SPI1:
1032 reg = &clk->div_peric1;
1036 case PERIPH_ID_SPI2:
1037 reg = &clk->div_peric2;
1041 case PERIPH_ID_SPI3:
1042 reg = &clk->sclk_div_isp;
1046 case PERIPH_ID_SPI4:
1047 reg = &clk->sclk_div_isp;
1052 debug("%s: Unsupported peripheral ID %d\n", __func__,
1056 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1057 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1062 static unsigned long exynos4_get_i2c_clk(void)
1064 struct exynos4_clock *clk =
1065 (struct exynos4_clock *)samsung_get_base_clock();
1066 unsigned long sclk, aclk_100;
1069 sclk = get_pll_clk(APLL);
1071 ratio = (readl(&clk->div_top)) >> 4;
1073 aclk_100 = sclk / (ratio + 1);
1077 unsigned long get_pll_clk(int pllreg)
1079 if (cpu_is_exynos5())
1080 return exynos5_get_pll_clk(pllreg);
1082 if (proid_is_exynos4412())
1083 return exynos4x12_get_pll_clk(pllreg);
1084 return exynos4_get_pll_clk(pllreg);
1088 unsigned long get_arm_clk(void)
1090 if (cpu_is_exynos5())
1091 return exynos5_get_arm_clk();
1093 if (proid_is_exynos4412())
1094 return exynos4x12_get_arm_clk();
1095 return exynos4_get_arm_clk();
1099 unsigned long get_i2c_clk(void)
1101 if (cpu_is_exynos5()) {
1102 return exynos5_get_i2c_clk();
1103 } else if (cpu_is_exynos4()) {
1104 return exynos4_get_i2c_clk();
1106 debug("I2C clock is not set for this CPU\n");
1111 unsigned long get_pwm_clk(void)
1113 if (cpu_is_exynos5())
1114 return exynos5_get_pwm_clk();
1116 if (proid_is_exynos4412())
1117 return exynos4x12_get_pwm_clk();
1118 return exynos4_get_pwm_clk();
1122 unsigned long get_uart_clk(int dev_index)
1124 if (cpu_is_exynos5())
1125 return exynos5_get_uart_clk(dev_index);
1127 if (proid_is_exynos4412())
1128 return exynos4x12_get_uart_clk(dev_index);
1129 return exynos4_get_uart_clk(dev_index);
1133 void set_mmc_clk(int dev_index, unsigned int div)
1135 if (cpu_is_exynos5())
1136 exynos5_set_mmc_clk(dev_index, div);
1138 if (proid_is_exynos4412())
1139 exynos4x12_set_mmc_clk(dev_index, div);
1140 exynos4_set_mmc_clk(dev_index, div);
1144 unsigned long get_lcd_clk(void)
1146 if (cpu_is_exynos4())
1147 return exynos4_get_lcd_clk();
1149 return exynos5_get_lcd_clk();
1152 void set_lcd_clk(void)
1154 if (cpu_is_exynos4())
1155 exynos4_set_lcd_clk();
1157 exynos5_set_lcd_clk();
1160 void set_mipi_clk(void)
1162 if (cpu_is_exynos4())
1163 exynos4_set_mipi_clk();
1166 int set_spi_clk(int periph_id, unsigned int rate)
1168 if (cpu_is_exynos5())
1169 return exynos5_set_spi_clk(periph_id, rate);
1174 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
1177 if (cpu_is_exynos5())
1178 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
1183 void set_i2s_clk_source(void)
1185 if (cpu_is_exynos5())
1186 exynos5_set_i2s_clk_source();
1189 int set_epll_clk(unsigned long rate)
1191 if (cpu_is_exynos5())
1192 return exynos5_set_epll_clk(rate);