2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/arch/clock.h>
27 #include <asm/arch/clk.h>
28 #include <asm/arch/periph.h>
31 * This structure is to store the src bit, div bit and prediv bit
32 * positions of the peripheral clocks of the src and div registers
40 /* src_bit div_bit prediv_bit */
41 static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
73 /* Epll Clock division values to achive different frequency output */
74 static struct set_epll_con_val exynos5_epll_div[] = {
75 { 192000000, 0, 48, 3, 1, 0 },
76 { 180000000, 0, 45, 3, 1, 0 },
77 { 73728000, 1, 73, 3, 3, 47710 },
78 { 67737600, 1, 90, 4, 3, 20762 },
79 { 49152000, 0, 49, 3, 3, 9961 },
80 { 45158400, 0, 45, 3, 3, 10381 },
81 { 180633600, 0, 45, 3, 1, 10381 }
84 /* exynos: return pll clock frequency */
85 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
87 unsigned long m, p, s = 0, mask, fout;
90 * APLL_CON: MIDV [25:16]
91 * MPLL_CON: MIDV [25:16]
92 * EPLL_CON: MIDV [24:16]
93 * VPLL_CON: MIDV [24:16]
94 * BPLL_CON: MIDV [25:16]: Exynos5
96 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL)
101 m = (r >> 16) & mask;
108 freq = CONFIG_SYS_CLK_FREQ;
110 if (pllreg == EPLL) {
112 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
113 fout = (m + k / 65536) * (freq / (p * (1 << s)));
114 } else if (pllreg == VPLL) {
116 /* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
117 fout = (m + k / 1024) * (freq / (p * (1 << s)));
119 /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
120 fout = m * (freq / (p * (1 << s)));
126 /* exynos4: return pll clock frequency */
127 static unsigned long exynos4_get_pll_clk(int pllreg)
129 struct exynos4_clock *clk =
130 (struct exynos4_clock *)samsung_get_base_clock();
131 unsigned long r, k = 0;
135 r = readl(&clk->apll_con0);
138 r = readl(&clk->mpll_con0);
141 r = readl(&clk->epll_con0);
142 k = readl(&clk->epll_con1);
145 r = readl(&clk->vpll_con0);
146 k = readl(&clk->vpll_con1);
149 printf("Unsupported PLL (%d)\n", pllreg);
153 return exynos_get_pll_clk(pllreg, r, k);
156 /* exynos4x12: return pll clock frequency */
157 static unsigned long exynos4x12_get_pll_clk(int pllreg)
159 struct exynos4x12_clock *clk =
160 (struct exynos4x12_clock *)samsung_get_base_clock();
161 unsigned long r, k = 0;
165 r = readl(&clk->apll_con0);
168 r = readl(&clk->mpll_con0);
171 r = readl(&clk->epll_con0);
172 k = readl(&clk->epll_con1);
175 r = readl(&clk->vpll_con0);
176 k = readl(&clk->vpll_con1);
179 printf("Unsupported PLL (%d)\n", pllreg);
183 return exynos_get_pll_clk(pllreg, r, k);
186 /* exynos5: return pll clock frequency */
187 static unsigned long exynos5_get_pll_clk(int pllreg)
189 struct exynos5_clock *clk =
190 (struct exynos5_clock *)samsung_get_base_clock();
191 unsigned long r, k = 0, fout;
192 unsigned int pll_div2_sel, fout_sel;
196 r = readl(&clk->apll_con0);
199 r = readl(&clk->mpll_con0);
202 r = readl(&clk->epll_con0);
203 k = readl(&clk->epll_con1);
206 r = readl(&clk->vpll_con0);
207 k = readl(&clk->vpll_con1);
210 r = readl(&clk->bpll_con0);
213 printf("Unsupported PLL (%d)\n", pllreg);
217 fout = exynos_get_pll_clk(pllreg, r, k);
219 /* According to the user manual, in EVT1 MPLL and BPLL always gives
220 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
221 if (pllreg == MPLL || pllreg == BPLL) {
222 pll_div2_sel = readl(&clk->pll_div2_sel);
226 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
227 & MPLL_FOUT_SEL_MASK;
230 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
231 & BPLL_FOUT_SEL_MASK;
245 static unsigned long exynos5_get_periph_rate(int peripheral)
247 struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
248 unsigned long sclk, sub_clk;
249 unsigned int src, div, sub_div;
250 struct exynos5_clock *clk =
251 (struct exynos5_clock *)samsung_get_base_clock();
253 switch (peripheral) {
254 case PERIPH_ID_UART0:
255 case PERIPH_ID_UART1:
256 case PERIPH_ID_UART2:
257 case PERIPH_ID_UART3:
258 src = readl(&clk->src_peric0);
259 div = readl(&clk->div_peric0);
266 src = readl(&clk->src_peric0);
267 div = readl(&clk->div_peric3);
271 src = readl(&clk->src_peric1);
272 div = readl(&clk->div_peric1);
275 src = readl(&clk->src_peric1);
276 div = readl(&clk->div_peric2);
280 src = readl(&clk->sclk_src_isp);
281 div = readl(&clk->sclk_div_isp);
283 case PERIPH_ID_SDMMC0:
284 case PERIPH_ID_SDMMC1:
285 case PERIPH_ID_SDMMC2:
286 case PERIPH_ID_SDMMC3:
287 src = readl(&clk->src_fsys);
288 div = readl(&clk->div_fsys1);
298 sclk = exynos5_get_pll_clk(MPLL);
299 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
301 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
303 return (sclk / sub_div) / div;
305 debug("%s: invalid peripheral %d", __func__, peripheral);
309 src = (src >> bit_info->src_bit) & 0xf;
312 case EXYNOS_SRC_MPLL:
313 sclk = exynos5_get_pll_clk(MPLL);
315 case EXYNOS_SRC_EPLL:
316 sclk = exynos5_get_pll_clk(EPLL);
318 case EXYNOS_SRC_VPLL:
319 sclk = exynos5_get_pll_clk(VPLL);
325 /* Ratio clock division for this peripheral */
326 sub_div = (div >> bit_info->div_bit) & 0xf;
327 sub_clk = sclk / (sub_div + 1);
329 /* Pre-ratio clock division for SDMMC0 and 2 */
330 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
331 div = (div >> bit_info->prediv_bit) & 0xff;
332 return sub_clk / (div + 1);
338 unsigned long clock_get_periph_rate(int peripheral)
340 if (cpu_is_exynos5())
341 return exynos5_get_periph_rate(peripheral);
346 /* exynos4: return ARM clock frequency */
347 static unsigned long exynos4_get_arm_clk(void)
349 struct exynos4_clock *clk =
350 (struct exynos4_clock *)samsung_get_base_clock();
352 unsigned long armclk;
353 unsigned int core_ratio;
354 unsigned int core2_ratio;
356 div = readl(&clk->div_cpu0);
358 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
359 core_ratio = (div >> 0) & 0x7;
360 core2_ratio = (div >> 28) & 0x7;
362 armclk = get_pll_clk(APLL) / (core_ratio + 1);
363 armclk /= (core2_ratio + 1);
368 /* exynos4x12: return ARM clock frequency */
369 static unsigned long exynos4x12_get_arm_clk(void)
371 struct exynos4x12_clock *clk =
372 (struct exynos4x12_clock *)samsung_get_base_clock();
374 unsigned long armclk;
375 unsigned int core_ratio;
376 unsigned int core2_ratio;
378 div = readl(&clk->div_cpu0);
380 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
381 core_ratio = (div >> 0) & 0x7;
382 core2_ratio = (div >> 28) & 0x7;
384 armclk = get_pll_clk(APLL) / (core_ratio + 1);
385 armclk /= (core2_ratio + 1);
390 /* exynos5: return ARM clock frequency */
391 static unsigned long exynos5_get_arm_clk(void)
393 struct exynos5_clock *clk =
394 (struct exynos5_clock *)samsung_get_base_clock();
396 unsigned long armclk;
397 unsigned int arm_ratio;
398 unsigned int arm2_ratio;
400 div = readl(&clk->div_cpu0);
402 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
403 arm_ratio = (div >> 0) & 0x7;
404 arm2_ratio = (div >> 28) & 0x7;
406 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
407 armclk /= (arm2_ratio + 1);
412 /* exynos4: return pwm clock frequency */
413 static unsigned long exynos4_get_pwm_clk(void)
415 struct exynos4_clock *clk =
416 (struct exynos4_clock *)samsung_get_base_clock();
417 unsigned long pclk, sclk;
421 if (s5p_get_cpu_rev() == 0) {
426 sel = readl(&clk->src_peril0);
427 sel = (sel >> 24) & 0xf;
430 sclk = get_pll_clk(MPLL);
432 sclk = get_pll_clk(EPLL);
434 sclk = get_pll_clk(VPLL);
442 ratio = readl(&clk->div_peril3);
444 } else if (s5p_get_cpu_rev() == 1) {
445 sclk = get_pll_clk(MPLL);
450 pclk = sclk / (ratio + 1);
455 /* exynos4x12: return pwm clock frequency */
456 static unsigned long exynos4x12_get_pwm_clk(void)
458 unsigned long pclk, sclk;
461 sclk = get_pll_clk(MPLL);
464 pclk = sclk / (ratio + 1);
469 /* exynos4: return uart clock frequency */
470 static unsigned long exynos4_get_uart_clk(int dev_index)
472 struct exynos4_clock *clk =
473 (struct exynos4_clock *)samsung_get_base_clock();
474 unsigned long uclk, sclk;
487 sel = readl(&clk->src_peril0);
488 sel = (sel >> (dev_index << 2)) & 0xf;
491 sclk = get_pll_clk(MPLL);
493 sclk = get_pll_clk(EPLL);
495 sclk = get_pll_clk(VPLL);
504 * UART3_RATIO [12:15]
505 * UART4_RATIO [16:19]
506 * UART5_RATIO [23:20]
508 ratio = readl(&clk->div_peril0);
509 ratio = (ratio >> (dev_index << 2)) & 0xf;
511 uclk = sclk / (ratio + 1);
516 /* exynos4x12: return uart clock frequency */
517 static unsigned long exynos4x12_get_uart_clk(int dev_index)
519 struct exynos4x12_clock *clk =
520 (struct exynos4x12_clock *)samsung_get_base_clock();
521 unsigned long uclk, sclk;
533 sel = readl(&clk->src_peril0);
534 sel = (sel >> (dev_index << 2)) & 0xf;
537 sclk = get_pll_clk(MPLL);
539 sclk = get_pll_clk(EPLL);
541 sclk = get_pll_clk(VPLL);
550 * UART3_RATIO [12:15]
551 * UART4_RATIO [16:19]
553 ratio = readl(&clk->div_peril0);
554 ratio = (ratio >> (dev_index << 2)) & 0xf;
556 uclk = sclk / (ratio + 1);
561 /* exynos5: return uart clock frequency */
562 static unsigned long exynos5_get_uart_clk(int dev_index)
564 struct exynos5_clock *clk =
565 (struct exynos5_clock *)samsung_get_base_clock();
566 unsigned long uclk, sclk;
579 sel = readl(&clk->src_peric0);
580 sel = (sel >> (dev_index << 2)) & 0xf;
583 sclk = get_pll_clk(MPLL);
585 sclk = get_pll_clk(EPLL);
587 sclk = get_pll_clk(VPLL);
596 * UART3_RATIO [12:15]
597 * UART4_RATIO [16:19]
598 * UART5_RATIO [23:20]
600 ratio = readl(&clk->div_peric0);
601 ratio = (ratio >> (dev_index << 2)) & 0xf;
603 uclk = sclk / (ratio + 1);
608 static unsigned long exynos4_get_mmc_clk(int dev_index)
610 struct exynos4_clock *clk =
611 (struct exynos4_clock *)samsung_get_base_clock();
612 unsigned long uclk, sclk;
613 unsigned int sel, ratio, pre_ratio;
616 sel = readl(&clk->src_fsys);
617 sel = (sel >> (dev_index << 2)) & 0xf;
620 sclk = get_pll_clk(MPLL);
622 sclk = get_pll_clk(EPLL);
624 sclk = get_pll_clk(VPLL);
631 ratio = readl(&clk->div_fsys1);
632 pre_ratio = readl(&clk->div_fsys1);
636 ratio = readl(&clk->div_fsys2);
637 pre_ratio = readl(&clk->div_fsys2);
640 ratio = readl(&clk->div_fsys3);
641 pre_ratio = readl(&clk->div_fsys3);
647 if (dev_index == 1 || dev_index == 3)
650 ratio = (ratio >> shift) & 0xf;
651 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
652 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
657 static unsigned long exynos5_get_mmc_clk(int dev_index)
659 struct exynos5_clock *clk =
660 (struct exynos5_clock *)samsung_get_base_clock();
661 unsigned long uclk, sclk;
662 unsigned int sel, ratio, pre_ratio;
665 sel = readl(&clk->src_fsys);
666 sel = (sel >> (dev_index << 2)) & 0xf;
669 sclk = get_pll_clk(MPLL);
671 sclk = get_pll_clk(EPLL);
673 sclk = get_pll_clk(VPLL);
680 ratio = readl(&clk->div_fsys1);
681 pre_ratio = readl(&clk->div_fsys1);
685 ratio = readl(&clk->div_fsys2);
686 pre_ratio = readl(&clk->div_fsys2);
692 if (dev_index == 1 || dev_index == 3)
695 ratio = (ratio >> shift) & 0xf;
696 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
697 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
702 /* exynos4: set the mmc clock */
703 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
705 struct exynos4_clock *clk =
706 (struct exynos4_clock *)samsung_get_base_clock();
712 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
714 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
716 * MMC4_PRE_RATIO [15:8]
719 addr = (unsigned int)&clk->div_fsys1;
720 } else if (dev_index == 4) {
721 addr = (unsigned int)&clk->div_fsys3;
724 addr = (unsigned int)&clk->div_fsys2;
729 val &= ~(0xff << ((dev_index << 4) + 8));
730 val |= (div & 0xff) << ((dev_index << 4) + 8);
734 /* exynos4x12: set the mmc clock */
735 static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div)
737 struct exynos4x12_clock *clk =
738 (struct exynos4x12_clock *)samsung_get_base_clock();
744 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
746 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
749 addr = (unsigned int)&clk->div_fsys1;
751 addr = (unsigned int)&clk->div_fsys2;
756 val &= ~(0xff << ((dev_index << 4) + 8));
757 val |= (div & 0xff) << ((dev_index << 4) + 8);
761 /* exynos5: set the mmc clock */
762 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
764 struct exynos5_clock *clk =
765 (struct exynos5_clock *)samsung_get_base_clock();
771 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
773 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
776 addr = (unsigned int)&clk->div_fsys1;
778 addr = (unsigned int)&clk->div_fsys2;
783 val &= ~(0xff << ((dev_index << 4) + 8));
784 val |= (div & 0xff) << ((dev_index << 4) + 8);
788 /* get_lcd_clk: return lcd clock frequency */
789 static unsigned long exynos4_get_lcd_clk(void)
791 struct exynos4_clock *clk =
792 (struct exynos4_clock *)samsung_get_base_clock();
793 unsigned long pclk, sclk;
801 sel = readl(&clk->src_lcd0);
810 sclk = get_pll_clk(MPLL);
812 sclk = get_pll_clk(EPLL);
814 sclk = get_pll_clk(VPLL);
822 ratio = readl(&clk->div_lcd0);
825 pclk = sclk / (ratio + 1);
830 /* get_lcd_clk: return lcd clock frequency */
831 static unsigned long exynos5_get_lcd_clk(void)
833 struct exynos5_clock *clk =
834 (struct exynos5_clock *)samsung_get_base_clock();
835 unsigned long pclk, sclk;
843 sel = readl(&clk->src_disp1_0);
852 sclk = get_pll_clk(MPLL);
854 sclk = get_pll_clk(EPLL);
856 sclk = get_pll_clk(VPLL);
864 ratio = readl(&clk->div_disp1_0);
867 pclk = sclk / (ratio + 1);
872 void exynos4_set_lcd_clk(void)
874 struct exynos4_clock *clk =
875 (struct exynos4_clock *)samsung_get_base_clock();
876 unsigned int cfg = 0;
888 cfg = readl(&clk->gate_block);
890 writel(cfg, &clk->gate_block);
896 * MDNIE_PWM0_SEL [8:11]
898 * set lcd0 src clock 0x6: SCLK_MPLL
900 cfg = readl(&clk->src_lcd0);
903 writel(cfg, &clk->src_lcd0);
913 * Gating all clocks for FIMD0
915 cfg = readl(&clk->gate_ip_lcd0);
917 writel(cfg, &clk->gate_ip_lcd0);
923 * MDNIE_PWM0_RATIO [11:8]
924 * MDNIE_PWM_PRE_RATIO [15:12]
925 * MIPI0_RATIO [19:16]
926 * MIPI0_PRE_RATIO [23:20]
931 writel(cfg, &clk->div_lcd0);
934 void exynos5_set_lcd_clk(void)
936 struct exynos5_clock *clk =
937 (struct exynos5_clock *)samsung_get_base_clock();
938 unsigned int cfg = 0;
950 cfg = readl(&clk->gate_block);
952 writel(cfg, &clk->gate_block);
958 * MDNIE_PWM0_SEL [8:11]
960 * set lcd0 src clock 0x6: SCLK_MPLL
962 cfg = readl(&clk->src_disp1_0);
965 writel(cfg, &clk->src_disp1_0);
975 * Gating all clocks for FIMD0
977 cfg = readl(&clk->gate_ip_disp1);
979 writel(cfg, &clk->gate_ip_disp1);
985 * MDNIE_PWM0_RATIO [11:8]
986 * MDNIE_PWM_PRE_RATIO [15:12]
987 * MIPI0_RATIO [19:16]
988 * MIPI0_PRE_RATIO [23:20]
993 writel(cfg, &clk->div_disp1_0);
996 void exynos4_set_mipi_clk(void)
998 struct exynos4_clock *clk =
999 (struct exynos4_clock *)samsung_get_base_clock();
1000 unsigned int cfg = 0;
1006 * MDNIE_PWM0_SEL [8:11]
1008 * set mipi0 src clock 0x6: SCLK_MPLL
1010 cfg = readl(&clk->src_lcd0);
1011 cfg &= ~(0xf << 12);
1013 writel(cfg, &clk->src_lcd0);
1019 * MDNIE_PWM0_MASK [8]
1021 * set src mask mipi0 0x1: Unmask
1023 cfg = readl(&clk->src_mask_lcd0);
1025 writel(cfg, &clk->src_mask_lcd0);
1035 * Gating all clocks for MIPI0
1037 cfg = readl(&clk->gate_ip_lcd0);
1039 writel(cfg, &clk->gate_ip_lcd0);
1044 * MDNIE0_RATIO [7:4]
1045 * MDNIE_PWM0_RATIO [11:8]
1046 * MDNIE_PWM_PRE_RATIO [15:12]
1047 * MIPI0_RATIO [19:16]
1048 * MIPI0_PRE_RATIO [23:20]
1051 cfg &= ~(0xf << 16);
1053 writel(cfg, &clk->div_lcd0);
1059 * exynos5: obtaining the I2C clock
1061 static unsigned long exynos5_get_i2c_clk(void)
1063 struct exynos5_clock *clk =
1064 (struct exynos5_clock *)samsung_get_base_clock();
1065 unsigned long aclk_66, aclk_66_pre, sclk;
1068 sclk = get_pll_clk(MPLL);
1070 ratio = (readl(&clk->div_top1)) >> 24;
1072 aclk_66_pre = sclk / (ratio + 1);
1073 ratio = readl(&clk->div_top0);
1075 aclk_66 = aclk_66_pre / (ratio + 1);
1079 int exynos5_set_epll_clk(unsigned long rate)
1081 unsigned int epll_con, epll_con_k;
1083 unsigned int lockcnt;
1085 struct exynos5_clock *clk =
1086 (struct exynos5_clock *)samsung_get_base_clock();
1088 epll_con = readl(&clk->epll_con0);
1089 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1090 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1091 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1092 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1093 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1095 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1096 if (exynos5_epll_div[i].freq_out == rate)
1100 if (i == ARRAY_SIZE(exynos5_epll_div))
1103 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1104 epll_con |= exynos5_epll_div[i].en_lock_det <<
1105 EPLL_CON0_LOCK_DET_EN_SHIFT;
1106 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1107 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1108 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1111 * Required period ( in cycles) to genarate a stable clock output.
1112 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1113 * frequency input (as per spec)
1115 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1117 writel(lockcnt, &clk->epll_lock);
1118 writel(epll_con, &clk->epll_con0);
1119 writel(epll_con_k, &clk->epll_con1);
1121 start = get_timer(0);
1123 while (!(readl(&clk->epll_con0) &
1124 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1125 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1126 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1133 void exynos5_set_i2s_clk_source(void)
1135 struct exynos5_clock *clk =
1136 (struct exynos5_clock *)samsung_get_base_clock();
1138 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1139 (CLK_SRC_SCLK_EPLL));
1142 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1143 unsigned int dst_frq)
1145 struct exynos5_clock *clk =
1146 (struct exynos5_clock *)samsung_get_base_clock();
1149 if ((dst_frq == 0) || (src_frq == 0)) {
1150 debug("%s: Invalid requency input for prescaler\n", __func__);
1151 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1155 div = (src_frq / dst_frq);
1156 if (div > AUDIO_1_RATIO_MASK) {
1157 debug("%s: Frequency ratio is out of range\n", __func__);
1158 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1161 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1162 (div & AUDIO_1_RATIO_MASK));
1167 * Linearly searches for the most accurate main and fine stage clock scalars
1168 * (divisors) for a specified target frequency and scalar bit sizes by checking
1169 * all multiples of main_scalar_bits values. Will always return scalars up to or
1170 * slower than target.
1172 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1173 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1174 * @param input_freq Clock frequency to be scaled in Hz
1175 * @param target_freq Desired clock frequency in Hz
1176 * @param best_fine_scalar Pointer to store the fine stage divisor
1178 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1181 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1182 unsigned int fine_scalar_bits, unsigned int input_rate,
1183 unsigned int target_rate, unsigned int *best_fine_scalar)
1186 int best_main_scalar = -1;
1187 unsigned int best_error = target_rate;
1188 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1189 const unsigned int loops = 1 << main_scaler_bits;
1191 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1194 assert(best_fine_scalar != NULL);
1195 assert(main_scaler_bits <= fine_scalar_bits);
1197 *best_fine_scalar = 1;
1199 if (input_rate == 0 || target_rate == 0)
1202 if (target_rate >= input_rate)
1205 for (i = 1; i <= loops; i++) {
1206 const unsigned int effective_div = max(min(input_rate / i /
1207 target_rate, cap), 1);
1208 const unsigned int effective_rate = input_rate / i /
1210 const int error = target_rate - effective_rate;
1212 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1213 effective_rate, error);
1215 if (error >= 0 && error <= best_error) {
1217 best_main_scalar = i;
1218 *best_fine_scalar = effective_div;
1222 return best_main_scalar;
1225 static int exynos5_set_spi_clk(enum periph_id periph_id,
1228 struct exynos5_clock *clk =
1229 (struct exynos5_clock *)samsung_get_base_clock();
1232 unsigned shift, pre_shift;
1233 unsigned mask = 0xff;
1236 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1238 debug("%s: Cannot set clock rate for periph %d",
1239 __func__, periph_id);
1245 switch (periph_id) {
1246 case PERIPH_ID_SPI0:
1247 reg = &clk->div_peric1;
1251 case PERIPH_ID_SPI1:
1252 reg = &clk->div_peric1;
1256 case PERIPH_ID_SPI2:
1257 reg = &clk->div_peric2;
1261 case PERIPH_ID_SPI3:
1262 reg = &clk->sclk_div_isp;
1266 case PERIPH_ID_SPI4:
1267 reg = &clk->sclk_div_isp;
1272 debug("%s: Unsupported peripheral ID %d\n", __func__,
1276 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1277 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1282 static unsigned long exynos4_get_i2c_clk(void)
1284 struct exynos4_clock *clk =
1285 (struct exynos4_clock *)samsung_get_base_clock();
1286 unsigned long sclk, aclk_100;
1289 sclk = get_pll_clk(APLL);
1291 ratio = (readl(&clk->div_top)) >> 4;
1293 aclk_100 = sclk / (ratio + 1);
1297 unsigned long get_pll_clk(int pllreg)
1299 if (cpu_is_exynos5())
1300 return exynos5_get_pll_clk(pllreg);
1302 if (proid_is_exynos4412())
1303 return exynos4x12_get_pll_clk(pllreg);
1304 return exynos4_get_pll_clk(pllreg);
1308 unsigned long get_arm_clk(void)
1310 if (cpu_is_exynos5())
1311 return exynos5_get_arm_clk();
1313 if (proid_is_exynos4412())
1314 return exynos4x12_get_arm_clk();
1315 return exynos4_get_arm_clk();
1319 unsigned long get_i2c_clk(void)
1321 if (cpu_is_exynos5()) {
1322 return exynos5_get_i2c_clk();
1323 } else if (cpu_is_exynos4()) {
1324 return exynos4_get_i2c_clk();
1326 debug("I2C clock is not set for this CPU\n");
1331 unsigned long get_pwm_clk(void)
1333 if (cpu_is_exynos5())
1334 return clock_get_periph_rate(PERIPH_ID_PWM0);
1336 if (proid_is_exynos4412())
1337 return exynos4x12_get_pwm_clk();
1338 return exynos4_get_pwm_clk();
1342 unsigned long get_uart_clk(int dev_index)
1344 if (cpu_is_exynos5())
1345 return exynos5_get_uart_clk(dev_index);
1347 if (proid_is_exynos4412())
1348 return exynos4x12_get_uart_clk(dev_index);
1349 return exynos4_get_uart_clk(dev_index);
1353 unsigned long get_mmc_clk(int dev_index)
1355 if (cpu_is_exynos5())
1356 return exynos5_get_mmc_clk(dev_index);
1358 return exynos4_get_mmc_clk(dev_index);
1361 void set_mmc_clk(int dev_index, unsigned int div)
1363 if (cpu_is_exynos5())
1364 exynos5_set_mmc_clk(dev_index, div);
1366 if (proid_is_exynos4412())
1367 exynos4x12_set_mmc_clk(dev_index, div);
1368 exynos4_set_mmc_clk(dev_index, div);
1372 unsigned long get_lcd_clk(void)
1374 if (cpu_is_exynos4())
1375 return exynos4_get_lcd_clk();
1377 return exynos5_get_lcd_clk();
1380 void set_lcd_clk(void)
1382 if (cpu_is_exynos4())
1383 exynos4_set_lcd_clk();
1385 exynos5_set_lcd_clk();
1388 void set_mipi_clk(void)
1390 if (cpu_is_exynos4())
1391 exynos4_set_mipi_clk();
1394 int set_spi_clk(int periph_id, unsigned int rate)
1396 if (cpu_is_exynos5())
1397 return exynos5_set_spi_clk(periph_id, rate);
1402 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
1405 if (cpu_is_exynos5())
1406 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq);
1411 void set_i2s_clk_source(void)
1413 if (cpu_is_exynos5())
1414 exynos5_set_i2s_clk_source();
1417 int set_epll_clk(unsigned long rate)
1419 if (cpu_is_exynos5())
1420 return exynos5_set_epll_clk(rate);