git.sur5r.net Git - u-boot/blob - arch/arm/cpu/armv7/exynos/clock.c

   1 /*
   2  * Copyright (C) 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/clk.h>
  12 #include <asm/arch/periph.h>
  13
  14 #define PLL_DIV_1024    1024
  15 #define PLL_DIV_65535   65535
  16 #define PLL_DIV_65536   65536
  17
  18 /* *
  19  * This structure is to store the src bit, div bit and prediv bit
  20  * positions of the peripheral clocks of the src and div registers
  21  */
  22 struct clk_bit_info {
  23         enum periph_id id;
  24         int8_t src_bit;
  25         int8_t div_bit;
  26         int8_t prediv_bit;
  27 };
  28
  29 /* periph_id src_bit div_bit prediv_bit */
  30 static struct clk_bit_info exynos5_bit_info[] = {
  31         {PERIPH_ID_UART0,       0,      0,      -1},
  32         {PERIPH_ID_UART1,       4,      4,      -1},
  33         {PERIPH_ID_UART2,       8,      8,      -1},
  34         {PERIPH_ID_UART3,       12,     12,     -1},
  35         {PERIPH_ID_I2C0,        -1,     24,     0},
  36         {PERIPH_ID_I2C1,        -1,     24,     0},
  37         {PERIPH_ID_I2C2,        -1,     24,     0},
  38         {PERIPH_ID_I2C3,        -1,     24,     0},
  39         {PERIPH_ID_I2C4,        -1,     24,     0},
  40         {PERIPH_ID_I2C5,        -1,     24,     0},
  41         {PERIPH_ID_I2C6,        -1,     24,     0},
  42         {PERIPH_ID_I2C7,        -1,     24,     0},
  43         {PERIPH_ID_SPI0,        16,     0,      8},
  44         {PERIPH_ID_SPI1,        20,     16,     24},
  45         {PERIPH_ID_SPI2,        24,     0,      8},
  46         {PERIPH_ID_SDMMC0,      0,      0,      8},
  47         {PERIPH_ID_SDMMC1,      4,      16,     24},
  48         {PERIPH_ID_SDMMC2,      8,      0,      8},
  49         {PERIPH_ID_SDMMC3,      12,     16,     24},
  50         {PERIPH_ID_I2S0,        0,      0,      4},
  51         {PERIPH_ID_I2S1,        4,      12,     16},
  52         {PERIPH_ID_SPI3,        0,      0,      4},
  53         {PERIPH_ID_SPI4,        4,      12,     16},
  54         {PERIPH_ID_SDMMC4,      16,     0,      8},
  55         {PERIPH_ID_PWM0,        24,     0,      -1},
  56         {PERIPH_ID_PWM1,        24,     0,      -1},
  57         {PERIPH_ID_PWM2,        24,     0,      -1},
  58         {PERIPH_ID_PWM3,        24,     0,      -1},
  59         {PERIPH_ID_PWM4,        24,     0,      -1},
  60
  61         {PERIPH_ID_NONE,        -1,     -1,     -1},
  62 };
  63
  64 static struct clk_bit_info exynos542x_bit_info[] = {
  65         {PERIPH_ID_UART0,       4,      8,      -1},
  66         {PERIPH_ID_UART1,       8,      12,     -1},
  67         {PERIPH_ID_UART2,       12,     16,     -1},
  68         {PERIPH_ID_UART3,       16,     20,     -1},
  69         {PERIPH_ID_I2C0,        -1,     8,      -1},
  70         {PERIPH_ID_I2C1,        -1,     8,      -1},
  71         {PERIPH_ID_I2C2,        -1,     8,      -1},
  72         {PERIPH_ID_I2C3,        -1,     8,      -1},
  73         {PERIPH_ID_I2C4,        -1,     8,      -1},
  74         {PERIPH_ID_I2C5,        -1,     8,      -1},
  75         {PERIPH_ID_I2C6,        -1,     8,      -1},
  76         {PERIPH_ID_I2C7,        -1,     8,      -1},
  77         {PERIPH_ID_SPI0,        20,     20,     8},
  78         {PERIPH_ID_SPI1,        24,     24,     16},
  79         {PERIPH_ID_SPI2,        28,     28,     24},
  80         {PERIPH_ID_SDMMC0,      8,      0,      -1},
  81         {PERIPH_ID_SDMMC1,      12,     10,     -1},
  82         {PERIPH_ID_SDMMC2,      16,     20,     -1},
  83         {PERIPH_ID_I2C8,        -1,     8,      -1},
  84         {PERIPH_ID_I2C9,        -1,     8,      -1},
  85         {PERIPH_ID_I2S0,        0,      0,      4},
  86         {PERIPH_ID_I2S1,        4,      12,     16},
  87         {PERIPH_ID_SPI3,        12,     16,     0},
  88         {PERIPH_ID_SPI4,        16,     20,     8},
  89         {PERIPH_ID_PWM0,        24,     28,     -1},
  90         {PERIPH_ID_PWM1,        24,     28,     -1},
  91         {PERIPH_ID_PWM2,        24,     28,     -1},
  92         {PERIPH_ID_PWM3,        24,     28,     -1},
  93         {PERIPH_ID_PWM4,        24,     28,     -1},
  94         {PERIPH_ID_I2C10,       -1,     8,      -1},
  95
  96         {PERIPH_ID_NONE,        -1,     -1,     -1},
  97 };
  98
  99 /* Epll Clock division values to achive different frequency output */
 100 static struct set_epll_con_val exynos5_epll_div[] = {
 101         { 192000000, 0, 48, 3, 1, 0 },
 102         { 180000000, 0, 45, 3, 1, 0 },
 103         {  73728000, 1, 73, 3, 3, 47710 },
 104         {  67737600, 1, 90, 4, 3, 20762 },
 105         {  49152000, 0, 49, 3, 3, 9961 },
 106         {  45158400, 0, 45, 3, 3, 10381 },
 107         { 180633600, 0, 45, 3, 1, 10381 }
 108 };
 109
 110 /* exynos: return pll clock frequency */
 111 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
 112 {
 113         unsigned long m, p, s = 0, mask, fout;
 114         unsigned int div;
 115         unsigned int freq;
 116         /*
 117          * APLL_CON: MIDV [25:16]
 118          * MPLL_CON: MIDV [25:16]
 119          * EPLL_CON: MIDV [24:16]
 120          * VPLL_CON: MIDV [24:16]
 121          * BPLL_CON: MIDV [25:16]: Exynos5
 122          */
 123         if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
 124             pllreg == SPLL)
 125                 mask = 0x3ff;
 126         else
 127                 mask = 0x1ff;
 128
 129         m = (r >> 16) & mask;
 130
 131         /* PDIV [13:8] */
 132         p = (r >> 8) & 0x3f;
 133         /* SDIV [2:0] */
 134         s = r & 0x7;
 135
 136         freq = CONFIG_SYS_CLK_FREQ;
 137
 138         if (pllreg == EPLL || pllreg == RPLL) {
 139                 k = k & 0xffff;
 140                 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
 141                 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
 142         } else if (pllreg == VPLL) {
 143                 k = k & 0xfff;
 144
 145                 /*
 146                  * Exynos4210
 147                  * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
 148                  *
 149                  * Exynos4412
 150                  * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
 151                  *
 152                  * Exynos5250
 153                  * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
 154                  */
 155                 if (proid_is_exynos4210())
 156                         div = PLL_DIV_1024;
 157                 else if (proid_is_exynos4412())
 158                         div = PLL_DIV_65535;
 159                 else if (proid_is_exynos5250() || proid_is_exynos5420()
 160                          || proid_is_exynos5800())
 161                         div = PLL_DIV_65536;
 162                 else
 163                         return 0;
 164
 165                 fout = (m + k / div) * (freq / (p * (1 << s)));
 166         } else {
 167                 /*
 168                  * Exynos4412 / Exynos5250
 169                  * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
 170                  *
 171                  * Exynos4210
 172                  * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
 173                  */
 174                 if (proid_is_exynos4210())
 175                         fout = m * (freq / (p * (1 << (s - 1))));
 176                 else
 177                         fout = m * (freq / (p * (1 << s)));
 178         }
 179         return fout;
 180 }
 181
 182 /* exynos4: return pll clock frequency */
 183 static unsigned long exynos4_get_pll_clk(int pllreg)
 184 {
 185         struct exynos4_clock *clk =
 186                 (struct exynos4_clock *)samsung_get_base_clock();
 187         unsigned long r, k = 0;
 188
 189         switch (pllreg) {
 190         case APLL:
 191                 r = readl(&clk->apll_con0);
 192                 break;
 193         case MPLL:
 194                 r = readl(&clk->mpll_con0);
 195                 break;
 196         case EPLL:
 197                 r = readl(&clk->epll_con0);
 198                 k = readl(&clk->epll_con1);
 199                 break;
 200         case VPLL:
 201                 r = readl(&clk->vpll_con0);
 202                 k = readl(&clk->vpll_con1);
 203                 break;
 204         default:
 205                 printf("Unsupported PLL (%d)\n", pllreg);
 206                 return 0;
 207         }
 208
 209         return exynos_get_pll_clk(pllreg, r, k);
 210 }
 211
 212 /* exynos4x12: return pll clock frequency */
 213 static unsigned long exynos4x12_get_pll_clk(int pllreg)
 214 {
 215         struct exynos4x12_clock *clk =
 216                 (struct exynos4x12_clock *)samsung_get_base_clock();
 217         unsigned long r, k = 0;
 218
 219         switch (pllreg) {
 220         case APLL:
 221                 r = readl(&clk->apll_con0);
 222                 break;
 223         case MPLL:
 224                 r = readl(&clk->mpll_con0);
 225                 break;
 226         case EPLL:
 227                 r = readl(&clk->epll_con0);
 228                 k = readl(&clk->epll_con1);
 229                 break;
 230         case VPLL:
 231                 r = readl(&clk->vpll_con0);
 232                 k = readl(&clk->vpll_con1);
 233                 break;
 234         default:
 235                 printf("Unsupported PLL (%d)\n", pllreg);
 236                 return 0;
 237         }
 238
 239         return exynos_get_pll_clk(pllreg, r, k);
 240 }
 241
 242 /* exynos5: return pll clock frequency */
 243 static unsigned long exynos5_get_pll_clk(int pllreg)
 244 {
 245         struct exynos5_clock *clk =
 246                 (struct exynos5_clock *)samsung_get_base_clock();
 247         unsigned long r, k = 0, fout;
 248         unsigned int pll_div2_sel, fout_sel;
 249
 250         switch (pllreg) {
 251         case APLL:
 252                 r = readl(&clk->apll_con0);
 253                 break;
 254         case MPLL:
 255                 r = readl(&clk->mpll_con0);
 256                 break;
 257         case EPLL:
 258                 r = readl(&clk->epll_con0);
 259                 k = readl(&clk->epll_con1);
 260                 break;
 261         case VPLL:
 262                 r = readl(&clk->vpll_con0);
 263                 k = readl(&clk->vpll_con1);
 264                 break;
 265         case BPLL:
 266                 r = readl(&clk->bpll_con0);
 267                 break;
 268         default:
 269                 printf("Unsupported PLL (%d)\n", pllreg);
 270                 return 0;
 271         }
 272
 273         fout = exynos_get_pll_clk(pllreg, r, k);
 274
 275         /* According to the user manual, in EVT1 MPLL and BPLL always gives
 276          * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
 277         if (pllreg == MPLL || pllreg == BPLL) {
 278                 pll_div2_sel = readl(&clk->pll_div2_sel);
 279
 280                 switch (pllreg) {
 281                 case MPLL:
 282                         fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
 283                                         & MPLL_FOUT_SEL_MASK;
 284                         break;
 285                 case BPLL:
 286                         fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
 287                                         & BPLL_FOUT_SEL_MASK;
 288                         break;
 289                 default:
 290                         fout_sel = -1;
 291                         break;
 292                 }
 293
 294                 if (fout_sel == 0)
 295                         fout /= 2;
 296         }
 297
 298         return fout;
 299 }
 300
 301 /* exynos542x: return pll clock frequency */
 302 static unsigned long exynos542x_get_pll_clk(int pllreg)
 303 {
 304         struct exynos5420_clock *clk =
 305                 (struct exynos5420_clock *)samsung_get_base_clock();
 306         unsigned long r, k = 0;
 307
 308         switch (pllreg) {
 309         case APLL:
 310                 r = readl(&clk->apll_con0);
 311                 break;
 312         case MPLL:
 313                 r = readl(&clk->mpll_con0);
 314                 break;
 315         case EPLL:
 316                 r = readl(&clk->epll_con0);
 317                 k = readl(&clk->epll_con1);
 318                 break;
 319         case VPLL:
 320                 r = readl(&clk->vpll_con0);
 321                 k = readl(&clk->vpll_con1);
 322                 break;
 323         case BPLL:
 324                 r = readl(&clk->bpll_con0);
 325                 break;
 326         case RPLL:
 327                 r = readl(&clk->rpll_con0);
 328                 k = readl(&clk->rpll_con1);
 329                 break;
 330         case SPLL:
 331                 r = readl(&clk->spll_con0);
 332                 break;
 333         default:
 334                 printf("Unsupported PLL (%d)\n", pllreg);
 335                 return 0;
 336         }
 337
 338         return exynos_get_pll_clk(pllreg, r, k);
 339 }
 340
 341 static struct clk_bit_info *get_clk_bit_info(int peripheral)
 342 {
 343         int i;
 344         struct clk_bit_info *info;
 345
 346         if (proid_is_exynos5420() || proid_is_exynos5800())
 347                 info = exynos542x_bit_info;
 348         else
 349                 info = exynos5_bit_info;
 350
 351         for (i = 0; info[i].id != PERIPH_ID_NONE; i++) {
 352                 if (info[i].id == peripheral)
 353                         break;
 354         }
 355
 356         if (info[i].id == PERIPH_ID_NONE)
 357                 debug("ERROR: Peripheral ID %d not found\n", peripheral);
 358
 359         return &info[i];
 360 }
 361
 362 static unsigned long exynos5_get_periph_rate(int peripheral)
 363 {
 364         struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
 365         unsigned long sclk, sub_clk = 0;
 366         unsigned int src, div, sub_div = 0;
 367         struct exynos5_clock *clk =
 368                         (struct exynos5_clock *)samsung_get_base_clock();
 369
 370         switch (peripheral) {
 371         case PERIPH_ID_UART0:
 372         case PERIPH_ID_UART1:
 373         case PERIPH_ID_UART2:
 374         case PERIPH_ID_UART3:
 375                 src = readl(&clk->src_peric0);
 376                 div = readl(&clk->div_peric0);
 377                 break;
 378         case PERIPH_ID_PWM0:
 379         case PERIPH_ID_PWM1:
 380         case PERIPH_ID_PWM2:
 381         case PERIPH_ID_PWM3:
 382         case PERIPH_ID_PWM4:
 383                 src = readl(&clk->src_peric0);
 384                 div = readl(&clk->div_peric3);
 385                 break;
 386         case PERIPH_ID_I2S0:
 387                 src = readl(&clk->src_mau);
 388                 div = readl(&clk->div_mau);
 389         case PERIPH_ID_SPI0:
 390         case PERIPH_ID_SPI1:
 391                 src = readl(&clk->src_peric1);
 392                 div = readl(&clk->div_peric1);
 393                 break;
 394         case PERIPH_ID_SPI2:
 395                 src = readl(&clk->src_peric1);
 396                 div = readl(&clk->div_peric2);
 397                 break;
 398         case PERIPH_ID_SPI3:
 399         case PERIPH_ID_SPI4:
 400                 src = readl(&clk->sclk_src_isp);
 401                 div = readl(&clk->sclk_div_isp);
 402                 break;
 403         case PERIPH_ID_SDMMC0:
 404         case PERIPH_ID_SDMMC1:
 405                 src = readl(&clk->src_fsys);
 406                 div = readl(&clk->div_fsys1);
 407                 break;
 408         case PERIPH_ID_SDMMC2:
 409         case PERIPH_ID_SDMMC3:
 410                 src = readl(&clk->src_fsys);
 411                 div = readl(&clk->div_fsys2);
 412                 break;
 413         case PERIPH_ID_I2C0:
 414         case PERIPH_ID_I2C1:
 415         case PERIPH_ID_I2C2:
 416         case PERIPH_ID_I2C3:
 417         case PERIPH_ID_I2C4:
 418         case PERIPH_ID_I2C5:
 419         case PERIPH_ID_I2C6:
 420         case PERIPH_ID_I2C7:
 421                 sclk = exynos5_get_pll_clk(MPLL);
 422                 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
 423                                                                 & 0x7) + 1;
 424                 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
 425                                                                 & 0x7) + 1;
 426                 return (sclk / sub_div) / div;
 427         default:
 428                 debug("%s: invalid peripheral %d", __func__, peripheral);
 429                 return -1;
 430         };
 431
 432         if (bit_info->src_bit >= 0)
 433                 src = (src >> bit_info->src_bit) & 0xf;
 434
 435         switch (src) {
 436         case EXYNOS_SRC_MPLL:
 437                 sclk = exynos5_get_pll_clk(MPLL);
 438                 break;
 439         case EXYNOS_SRC_EPLL:
 440                 sclk = exynos5_get_pll_clk(EPLL);
 441                 break;
 442         case EXYNOS_SRC_VPLL:
 443                 sclk = exynos5_get_pll_clk(VPLL);
 444                 break;
 445         default:
 446                 return 0;
 447         }
 448
 449         /* Ratio clock division for this peripheral */
 450         if (bit_info->div_bit >= 0) {
 451                 sub_div = (div >> bit_info->div_bit) & 0xf;
 452                 sub_clk = sclk / (sub_div + 1);
 453         }
 454
 455         if (bit_info->prediv_bit >= 0) {
 456                 div = (div >> bit_info->prediv_bit) & 0xff;
 457                 return sub_clk / (div + 1);
 458         }
 459
 460         return sub_clk;
 461 }
 462
 463 static unsigned long exynos542x_get_periph_rate(int peripheral)
 464 {
 465         struct clk_bit_info *bit_info = get_clk_bit_info(peripheral);
 466         unsigned long sclk, sub_clk = 0;
 467         unsigned int src, div, sub_div = 0;
 468         struct exynos5420_clock *clk =
 469                         (struct exynos5420_clock *)samsung_get_base_clock();
 470
 471         switch (peripheral) {
 472         case PERIPH_ID_UART0:
 473         case PERIPH_ID_UART1:
 474         case PERIPH_ID_UART2:
 475         case PERIPH_ID_UART3:
 476         case PERIPH_ID_PWM0:
 477         case PERIPH_ID_PWM1:
 478         case PERIPH_ID_PWM2:
 479         case PERIPH_ID_PWM3:
 480         case PERIPH_ID_PWM4:
 481                 src = readl(&clk->src_peric0);
 482                 div = readl(&clk->div_peric0);
 483                 break;
 484         case PERIPH_ID_SPI0:
 485         case PERIPH_ID_SPI1:
 486         case PERIPH_ID_SPI2:
 487                 src = readl(&clk->src_peric1);
 488                 div = readl(&clk->div_peric1);
 489                 sub_div = readl(&clk->div_peric4);
 490                 break;
 491         case PERIPH_ID_SPI3:
 492         case PERIPH_ID_SPI4:
 493                 src = readl(&clk->src_isp);
 494                 div = readl(&clk->div_isp1);
 495                 sub_div = readl(&clk->div_isp1);
 496                 break;
 497         case PERIPH_ID_SDMMC0:
 498         case PERIPH_ID_SDMMC1:
 499         case PERIPH_ID_SDMMC2:
 500         case PERIPH_ID_SDMMC3:
 501                 src = readl(&clk->src_fsys);
 502                 div = readl(&clk->div_fsys1);
 503                 break;
 504         case PERIPH_ID_I2C0:
 505         case PERIPH_ID_I2C1:
 506         case PERIPH_ID_I2C2:
 507         case PERIPH_ID_I2C3:
 508         case PERIPH_ID_I2C4:
 509         case PERIPH_ID_I2C5:
 510         case PERIPH_ID_I2C6:
 511         case PERIPH_ID_I2C7:
 512         case PERIPH_ID_I2C8:
 513         case PERIPH_ID_I2C9:
 514         case PERIPH_ID_I2C10:
 515                 sclk = exynos542x_get_pll_clk(MPLL);
 516                 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
 517                                                                 & 0x7) + 1;
 518                 return sclk / sub_div;
 519         default:
 520                 debug("%s: invalid peripheral %d", __func__, peripheral);
 521                 return -1;
 522         };
 523
 524         if (bit_info->src_bit >= 0)
 525                 src = (src >> bit_info->src_bit) & 0xf;
 526
 527         switch (src) {
 528         case EXYNOS542X_SRC_MPLL:
 529                 sclk = exynos542x_get_pll_clk(MPLL);
 530                 break;
 531         case EXYNOS542X_SRC_SPLL:
 532                 sclk = exynos542x_get_pll_clk(SPLL);
 533                 break;
 534         case EXYNOS542X_SRC_EPLL:
 535                 sclk = exynos542x_get_pll_clk(EPLL);
 536                 break;
 537         case EXYNOS542X_SRC_RPLL:
 538                 sclk = exynos542x_get_pll_clk(RPLL);
 539                 break;
 540         default:
 541                 return 0;
 542         }
 543
 544         /* Ratio clock division for this peripheral */
 545         if (bit_info->div_bit >= 0) {
 546                 div = (div >> bit_info->div_bit) & 0xf;
 547                 sub_clk = sclk / (div + 1);
 548         }
 549
 550         if (bit_info->prediv_bit >= 0) {
 551                 sub_div = (sub_div >> bit_info->prediv_bit) & 0xff;
 552                 return sub_clk / (sub_div + 1);
 553         }
 554
 555         return sub_clk;
 556 }
 557
 558 unsigned long clock_get_periph_rate(int peripheral)
 559 {
 560         if (cpu_is_exynos5()) {
 561                 if (proid_is_exynos5420() || proid_is_exynos5800())
 562                         return exynos542x_get_periph_rate(peripheral);
 563                 return exynos5_get_periph_rate(peripheral);
 564         } else {
 565                 return 0;
 566         }
 567 }
 568
 569 /* exynos4: return ARM clock frequency */
 570 static unsigned long exynos4_get_arm_clk(void)
 571 {
 572         struct exynos4_clock *clk =
 573                 (struct exynos4_clock *)samsung_get_base_clock();
 574         unsigned long div;
 575         unsigned long armclk;
 576         unsigned int core_ratio;
 577         unsigned int core2_ratio;
 578
 579         div = readl(&clk->div_cpu0);
 580
 581         /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
 582         core_ratio = (div >> 0) & 0x7;
 583         core2_ratio = (div >> 28) & 0x7;
 584
 585         armclk = get_pll_clk(APLL) / (core_ratio + 1);
 586         armclk /= (core2_ratio + 1);
 587
 588         return armclk;
 589 }
 590
 591 /* exynos4x12: return ARM clock frequency */
 592 static unsigned long exynos4x12_get_arm_clk(void)
 593 {
 594         struct exynos4x12_clock *clk =
 595                 (struct exynos4x12_clock *)samsung_get_base_clock();
 596         unsigned long div;
 597         unsigned long armclk;
 598         unsigned int core_ratio;
 599         unsigned int core2_ratio;
 600
 601         div = readl(&clk->div_cpu0);
 602
 603         /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
 604         core_ratio = (div >> 0) & 0x7;
 605         core2_ratio = (div >> 28) & 0x7;
 606
 607         armclk = get_pll_clk(APLL) / (core_ratio + 1);
 608         armclk /= (core2_ratio + 1);
 609
 610         return armclk;
 611 }
 612
 613 /* exynos5: return ARM clock frequency */
 614 static unsigned long exynos5_get_arm_clk(void)
 615 {
 616         struct exynos5_clock *clk =
 617                 (struct exynos5_clock *)samsung_get_base_clock();
 618         unsigned long div;
 619         unsigned long armclk;
 620         unsigned int arm_ratio;
 621         unsigned int arm2_ratio;
 622
 623         div = readl(&clk->div_cpu0);
 624
 625         /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 626         arm_ratio = (div >> 0) & 0x7;
 627         arm2_ratio = (div >> 28) & 0x7;
 628
 629         armclk = get_pll_clk(APLL) / (arm_ratio + 1);
 630         armclk /= (arm2_ratio + 1);
 631
 632         return armclk;
 633 }
 634
 635 /* exynos4: return pwm clock frequency */
 636 static unsigned long exynos4_get_pwm_clk(void)
 637 {
 638         struct exynos4_clock *clk =
 639                 (struct exynos4_clock *)samsung_get_base_clock();
 640         unsigned long pclk, sclk;
 641         unsigned int sel;
 642         unsigned int ratio;
 643
 644         if (s5p_get_cpu_rev() == 0) {
 645                 /*
 646                  * CLK_SRC_PERIL0
 647                  * PWM_SEL [27:24]
 648                  */
 649                 sel = readl(&clk->src_peril0);
 650                 sel = (sel >> 24) & 0xf;
 651
 652                 if (sel == 0x6)
 653                         sclk = get_pll_clk(MPLL);
 654                 else if (sel == 0x7)
 655                         sclk = get_pll_clk(EPLL);
 656                 else if (sel == 0x8)
 657                         sclk = get_pll_clk(VPLL);
 658                 else
 659                         return 0;
 660
 661                 /*
 662                  * CLK_DIV_PERIL3
 663                  * PWM_RATIO [3:0]
 664                  */
 665                 ratio = readl(&clk->div_peril3);
 666                 ratio = ratio & 0xf;
 667         } else if (s5p_get_cpu_rev() == 1) {
 668                 sclk = get_pll_clk(MPLL);
 669                 ratio = 8;
 670         } else
 671                 return 0;
 672
 673         pclk = sclk / (ratio + 1);
 674
 675         return pclk;
 676 }
 677
 678 /* exynos4x12: return pwm clock frequency */
 679 static unsigned long exynos4x12_get_pwm_clk(void)
 680 {
 681         unsigned long pclk, sclk;
 682         unsigned int ratio;
 683
 684         sclk = get_pll_clk(MPLL);
 685         ratio = 8;
 686
 687         pclk = sclk / (ratio + 1);
 688
 689         return pclk;
 690 }
 691
 692 /* exynos4: return uart clock frequency */
 693 static unsigned long exynos4_get_uart_clk(int dev_index)
 694 {
 695         struct exynos4_clock *clk =
 696                 (struct exynos4_clock *)samsung_get_base_clock();
 697         unsigned long uclk, sclk;
 698         unsigned int sel;
 699         unsigned int ratio;
 700
 701         /*
 702          * CLK_SRC_PERIL0
 703          * UART0_SEL [3:0]
 704          * UART1_SEL [7:4]
 705          * UART2_SEL [8:11]
 706          * UART3_SEL [12:15]
 707          * UART4_SEL [16:19]
 708          * UART5_SEL [23:20]
 709          */
 710         sel = readl(&clk->src_peril0);
 711         sel = (sel >> (dev_index << 2)) & 0xf;
 712
 713         if (sel == 0x6)
 714                 sclk = get_pll_clk(MPLL);
 715         else if (sel == 0x7)
 716                 sclk = get_pll_clk(EPLL);
 717         else if (sel == 0x8)
 718                 sclk = get_pll_clk(VPLL);
 719         else
 720                 return 0;
 721
 722         /*
 723          * CLK_DIV_PERIL0
 724          * UART0_RATIO [3:0]
 725          * UART1_RATIO [7:4]
 726          * UART2_RATIO [8:11]
 727          * UART3_RATIO [12:15]
 728          * UART4_RATIO [16:19]
 729          * UART5_RATIO [23:20]
 730          */
 731         ratio = readl(&clk->div_peril0);
 732         ratio = (ratio >> (dev_index << 2)) & 0xf;
 733
 734         uclk = sclk / (ratio + 1);
 735
 736         return uclk;
 737 }
 738
 739 /* exynos4x12: return uart clock frequency */
 740 static unsigned long exynos4x12_get_uart_clk(int dev_index)
 741 {
 742         struct exynos4x12_clock *clk =
 743                 (struct exynos4x12_clock *)samsung_get_base_clock();
 744         unsigned long uclk, sclk;
 745         unsigned int sel;
 746         unsigned int ratio;
 747
 748         /*
 749          * CLK_SRC_PERIL0
 750          * UART0_SEL [3:0]
 751          * UART1_SEL [7:4]
 752          * UART2_SEL [8:11]
 753          * UART3_SEL [12:15]
 754          * UART4_SEL [16:19]
 755          */
 756         sel = readl(&clk->src_peril0);
 757         sel = (sel >> (dev_index << 2)) & 0xf;
 758
 759         if (sel == 0x6)
 760                 sclk = get_pll_clk(MPLL);
 761         else if (sel == 0x7)
 762                 sclk = get_pll_clk(EPLL);
 763         else if (sel == 0x8)
 764                 sclk = get_pll_clk(VPLL);
 765         else
 766                 return 0;
 767
 768         /*
 769          * CLK_DIV_PERIL0
 770          * UART0_RATIO [3:0]
 771          * UART1_RATIO [7:4]
 772          * UART2_RATIO [8:11]
 773          * UART3_RATIO [12:15]
 774          * UART4_RATIO [16:19]
 775          */
 776         ratio = readl(&clk->div_peril0);
 777         ratio = (ratio >> (dev_index << 2)) & 0xf;
 778
 779         uclk = sclk / (ratio + 1);
 780
 781         return uclk;
 782 }
 783
 784 static unsigned long exynos4_get_mmc_clk(int dev_index)
 785 {
 786         struct exynos4_clock *clk =
 787                 (struct exynos4_clock *)samsung_get_base_clock();
 788         unsigned long uclk, sclk;
 789         unsigned int sel, ratio, pre_ratio;
 790         int shift = 0;
 791
 792         sel = readl(&clk->src_fsys);
 793         sel = (sel >> (dev_index << 2)) & 0xf;
 794
 795         if (sel == 0x6)
 796                 sclk = get_pll_clk(MPLL);
 797         else if (sel == 0x7)
 798                 sclk = get_pll_clk(EPLL);
 799         else if (sel == 0x8)
 800                 sclk = get_pll_clk(VPLL);
 801         else
 802                 return 0;
 803
 804         switch (dev_index) {
 805         case 0:
 806         case 1:
 807                 ratio = readl(&clk->div_fsys1);
 808                 pre_ratio = readl(&clk->div_fsys1);
 809                 break;
 810         case 2:
 811         case 3:
 812                 ratio = readl(&clk->div_fsys2);
 813                 pre_ratio = readl(&clk->div_fsys2);
 814                 break;
 815         case 4:
 816                 ratio = readl(&clk->div_fsys3);
 817                 pre_ratio = readl(&clk->div_fsys3);
 818                 break;
 819         default:
 820                 return 0;
 821         }
 822
 823         if (dev_index == 1 || dev_index == 3)
 824                 shift = 16;
 825
 826         ratio = (ratio >> shift) & 0xf;
 827         pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
 828         uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
 829
 830         return uclk;
 831 }
 832
 833 /* exynos4: set the mmc clock */
 834 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
 835 {
 836         struct exynos4_clock *clk =
 837                 (struct exynos4_clock *)samsung_get_base_clock();
 838         unsigned int addr, clear_bit, set_bit;
 839
 840         /*
 841          * CLK_DIV_FSYS1
 842          * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
 843          * CLK_DIV_FSYS2
 844          * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
 845          * CLK_DIV_FSYS3
 846          * MMC4_RATIO [3:0]
 847          */
 848         if (dev_index < 2) {
 849                 addr = (unsigned int)&clk->div_fsys1;
 850                 clear_bit = MASK_PRE_RATIO(dev_index);
 851                 set_bit = SET_PRE_RATIO(dev_index, div);
 852         } else if (dev_index == 4) {
 853                 addr = (unsigned int)&clk->div_fsys3;
 854                 dev_index -= 4;
 855                 /* MMC4 is controlled with the MMC4_RATIO value */
 856                 clear_bit = MASK_RATIO(dev_index);
 857                 set_bit = SET_RATIO(dev_index, div);
 858         } else {
 859                 addr = (unsigned int)&clk->div_fsys2;
 860                 dev_index -= 2;
 861                 clear_bit = MASK_PRE_RATIO(dev_index);
 862                 set_bit = SET_PRE_RATIO(dev_index, div);
 863         }
 864
 865         clrsetbits_le32(addr, clear_bit, set_bit);
 866 }
 867
 868 /* exynos5: set the mmc clock */
 869 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
 870 {
 871         struct exynos5_clock *clk =
 872                 (struct exynos5_clock *)samsung_get_base_clock();
 873         unsigned int addr;
 874
 875         /*
 876          * CLK_DIV_FSYS1
 877          * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
 878          * CLK_DIV_FSYS2
 879          * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
 880          */
 881         if (dev_index < 2) {
 882                 addr = (unsigned int)&clk->div_fsys1;
 883         } else {
 884                 addr = (unsigned int)&clk->div_fsys2;
 885                 dev_index -= 2;
 886         }
 887
 888         clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
 889                         (div & 0xff) << ((dev_index << 4) + 8));
 890 }
 891
 892 /* exynos5: set the mmc clock */
 893 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
 894 {
 895         struct exynos5420_clock *clk =
 896                 (struct exynos5420_clock *)samsung_get_base_clock();
 897         unsigned int addr;
 898         unsigned int shift;
 899
 900         /*
 901          * CLK_DIV_FSYS1
 902          * MMC0_RATIO [9:0]
 903          * MMC1_RATIO [19:10]
 904          * MMC2_RATIO [29:20]
 905          */
 906         addr = (unsigned int)&clk->div_fsys1;
 907         shift = dev_index * 10;
 908
 909         clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
 910 }
 911
 912 /* get_lcd_clk: return lcd clock frequency */
 913 static unsigned long exynos4_get_lcd_clk(void)
 914 {
 915         struct exynos4_clock *clk =
 916                 (struct exynos4_clock *)samsung_get_base_clock();
 917         unsigned long pclk, sclk;
 918         unsigned int sel;
 919         unsigned int ratio;
 920
 921         /*
 922          * CLK_SRC_LCD0
 923          * FIMD0_SEL [3:0]
 924          */
 925         sel = readl(&clk->src_lcd0);
 926         sel = sel & 0xf;
 927
 928         /*
 929          * 0x6: SCLK_MPLL
 930          * 0x7: SCLK_EPLL
 931          * 0x8: SCLK_VPLL
 932          */
 933         if (sel == 0x6)
 934                 sclk = get_pll_clk(MPLL);
 935         else if (sel == 0x7)
 936                 sclk = get_pll_clk(EPLL);
 937         else if (sel == 0x8)
 938                 sclk = get_pll_clk(VPLL);
 939         else
 940                 return 0;
 941
 942         /*
 943          * CLK_DIV_LCD0
 944          * FIMD0_RATIO [3:0]
 945          */
 946         ratio = readl(&clk->div_lcd0);
 947         ratio = ratio & 0xf;
 948
 949         pclk = sclk / (ratio + 1);
 950
 951         return pclk;
 952 }
 953
 954 /* get_lcd_clk: return lcd clock frequency */
 955 static unsigned long exynos5_get_lcd_clk(void)
 956 {
 957         struct exynos5_clock *clk =
 958                 (struct exynos5_clock *)samsung_get_base_clock();
 959         unsigned long pclk, sclk;
 960         unsigned int sel;
 961         unsigned int ratio;
 962
 963         /*
 964          * CLK_SRC_LCD0
 965          * FIMD0_SEL [3:0]
 966          */
 967         sel = readl(&clk->src_disp1_0);
 968         sel = sel & 0xf;
 969
 970         /*
 971          * 0x6: SCLK_MPLL
 972          * 0x7: SCLK_EPLL
 973          * 0x8: SCLK_VPLL
 974          */
 975         if (sel == 0x6)
 976                 sclk = get_pll_clk(MPLL);
 977         else if (sel == 0x7)
 978                 sclk = get_pll_clk(EPLL);
 979         else if (sel == 0x8)
 980                 sclk = get_pll_clk(VPLL);
 981         else
 982                 return 0;
 983
 984         /*
 985          * CLK_DIV_LCD0
 986          * FIMD0_RATIO [3:0]
 987          */
 988         ratio = readl(&clk->div_disp1_0);
 989         ratio = ratio & 0xf;
 990
 991         pclk = sclk / (ratio + 1);
 992
 993         return pclk;
 994 }
 995
 996 static unsigned long exynos5420_get_lcd_clk(void)
 997 {
 998         struct exynos5420_clock *clk =
 999                 (struct exynos5420_clock *)samsung_get_base_clock();
1000         unsigned long pclk, sclk;
1001         unsigned int sel;
1002         unsigned int ratio;
1003
1004         /*
1005          * CLK_SRC_DISP10
1006          * FIMD1_SEL [4]
1007          * 0: SCLK_RPLL
1008          * 1: SCLK_SPLL
1009          */
1010         sel = readl(&clk->src_disp10);
1011         sel &= (1 << 4);
1012
1013         if (sel)
1014                 sclk = get_pll_clk(SPLL);
1015         else
1016                 sclk = get_pll_clk(RPLL);
1017
1018         /*
1019          * CLK_DIV_DISP10
1020          * FIMD1_RATIO [3:0]
1021          */
1022         ratio = readl(&clk->div_disp10);
1023         ratio = ratio & 0xf;
1024
1025         pclk = sclk / (ratio + 1);
1026
1027         return pclk;
1028 }
1029
1030 void exynos4_set_lcd_clk(void)
1031 {
1032         struct exynos4_clock *clk =
1033             (struct exynos4_clock *)samsung_get_base_clock();
1034
1035         /*
1036          * CLK_GATE_BLOCK
1037          * CLK_CAM      [0]
1038          * CLK_TV       [1]
1039          * CLK_MFC      [2]
1040          * CLK_G3D      [3]
1041          * CLK_LCD0     [4]
1042          * CLK_LCD1     [5]
1043          * CLK_GPS      [7]
1044          */
1045         setbits_le32(&clk->gate_block, 1 << 4);
1046
1047         /*
1048          * CLK_SRC_LCD0
1049          * FIMD0_SEL            [3:0]
1050          * MDNIE0_SEL           [7:4]
1051          * MDNIE_PWM0_SEL       [8:11]
1052          * MIPI0_SEL            [12:15]
1053          * set lcd0 src clock 0x6: SCLK_MPLL
1054          */
1055         clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
1056
1057         /*
1058          * CLK_GATE_IP_LCD0
1059          * CLK_FIMD0            [0]
1060          * CLK_MIE0             [1]
1061          * CLK_MDNIE0           [2]
1062          * CLK_DSIM0            [3]
1063          * CLK_SMMUFIMD0        [4]
1064          * CLK_PPMULCD0         [5]
1065          * Gating all clocks for FIMD0
1066          */
1067         setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
1068
1069         /*
1070          * CLK_DIV_LCD0
1071          * FIMD0_RATIO          [3:0]
1072          * MDNIE0_RATIO         [7:4]
1073          * MDNIE_PWM0_RATIO     [11:8]
1074          * MDNIE_PWM_PRE_RATIO  [15:12]
1075          * MIPI0_RATIO          [19:16]
1076          * MIPI0_PRE_RATIO      [23:20]
1077          * set fimd ratio
1078          */
1079         clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
1080 }
1081
1082 void exynos5_set_lcd_clk(void)
1083 {
1084         struct exynos5_clock *clk =
1085             (struct exynos5_clock *)samsung_get_base_clock();
1086
1087         /*
1088          * CLK_GATE_BLOCK
1089          * CLK_CAM      [0]
1090          * CLK_TV       [1]
1091          * CLK_MFC      [2]
1092          * CLK_G3D      [3]
1093          * CLK_LCD0     [4]
1094          * CLK_LCD1     [5]
1095          * CLK_GPS      [7]
1096          */
1097         setbits_le32(&clk->gate_block, 1 << 4);
1098
1099         /*
1100          * CLK_SRC_LCD0
1101          * FIMD0_SEL            [3:0]
1102          * MDNIE0_SEL           [7:4]
1103          * MDNIE_PWM0_SEL       [8:11]
1104          * MIPI0_SEL            [12:15]
1105          * set lcd0 src clock 0x6: SCLK_MPLL
1106          */
1107         clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
1108
1109         /*
1110          * CLK_GATE_IP_LCD0
1111          * CLK_FIMD0            [0]
1112          * CLK_MIE0             [1]
1113          * CLK_MDNIE0           [2]
1114          * CLK_DSIM0            [3]
1115          * CLK_SMMUFIMD0        [4]
1116          * CLK_PPMULCD0         [5]
1117          * Gating all clocks for FIMD0
1118          */
1119         setbits_le32(&clk->gate_ip_disp1, 1 << 0);
1120
1121         /*
1122          * CLK_DIV_LCD0
1123          * FIMD0_RATIO          [3:0]
1124          * MDNIE0_RATIO         [7:4]
1125          * MDNIE_PWM0_RATIO     [11:8]
1126          * MDNIE_PWM_PRE_RATIO  [15:12]
1127          * MIPI0_RATIO          [19:16]
1128          * MIPI0_PRE_RATIO      [23:20]
1129          * set fimd ratio
1130          */
1131         clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
1132 }
1133
1134 void exynos5420_set_lcd_clk(void)
1135 {
1136         struct exynos5420_clock *clk =
1137                 (struct exynos5420_clock *)samsung_get_base_clock();
1138         unsigned int cfg;
1139
1140         /*
1141          * CLK_SRC_DISP10
1142          * FIMD1_SEL [4]
1143          * 0: SCLK_RPLL
1144          * 1: SCLK_SPLL
1145          */
1146         cfg = readl(&clk->src_disp10);
1147         cfg &= ~(0x1 << 4);
1148         cfg |= (0 << 4);
1149         writel(cfg, &clk->src_disp10);
1150
1151         /*
1152          * CLK_DIV_DISP10
1153          * FIMD1_RATIO          [3:0]
1154          */
1155         cfg = readl(&clk->div_disp10);
1156         cfg &= ~(0xf << 0);
1157         cfg |= (0 << 0);
1158         writel(cfg, &clk->div_disp10);
1159 }
1160
1161 void exynos4_set_mipi_clk(void)
1162 {
1163         struct exynos4_clock *clk =
1164             (struct exynos4_clock *)samsung_get_base_clock();
1165
1166         /*
1167          * CLK_SRC_LCD0
1168          * FIMD0_SEL            [3:0]
1169          * MDNIE0_SEL           [7:4]
1170          * MDNIE_PWM0_SEL       [8:11]
1171          * MIPI0_SEL            [12:15]
1172          * set mipi0 src clock 0x6: SCLK_MPLL
1173          */
1174         clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
1175
1176         /*
1177          * CLK_SRC_MASK_LCD0
1178          * FIMD0_MASK           [0]
1179          * MDNIE0_MASK          [4]
1180          * MDNIE_PWM0_MASK      [8]
1181          * MIPI0_MASK           [12]
1182          * set src mask mipi0 0x1: Unmask
1183          */
1184         setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
1185
1186         /*
1187          * CLK_GATE_IP_LCD0
1188          * CLK_FIMD0            [0]
1189          * CLK_MIE0             [1]
1190          * CLK_MDNIE0           [2]
1191          * CLK_DSIM0            [3]
1192          * CLK_SMMUFIMD0        [4]
1193          * CLK_PPMULCD0         [5]
1194          * Gating all clocks for MIPI0
1195          */
1196         setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
1197
1198         /*
1199          * CLK_DIV_LCD0
1200          * FIMD0_RATIO          [3:0]
1201          * MDNIE0_RATIO         [7:4]
1202          * MDNIE_PWM0_RATIO     [11:8]
1203          * MDNIE_PWM_PRE_RATIO  [15:12]
1204          * MIPI0_RATIO          [19:16]
1205          * MIPI0_PRE_RATIO      [23:20]
1206          * set mipi ratio
1207          */
1208         clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
1209 }
1210
1211 int exynos5_set_epll_clk(unsigned long rate)
1212 {
1213         unsigned int epll_con, epll_con_k;
1214         unsigned int i;
1215         unsigned int lockcnt;
1216         unsigned int start;
1217         struct exynos5_clock *clk =
1218                 (struct exynos5_clock *)samsung_get_base_clock();
1219
1220         epll_con = readl(&clk->epll_con0);
1221         epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1222                         EPLL_CON0_LOCK_DET_EN_SHIFT) |
1223                 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1224                 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1225                 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1226
1227         for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1228                 if (exynos5_epll_div[i].freq_out == rate)
1229                         break;
1230         }
1231
1232         if (i == ARRAY_SIZE(exynos5_epll_div))
1233                 return -1;
1234
1235         epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1236         epll_con |= exynos5_epll_div[i].en_lock_det <<
1237                                 EPLL_CON0_LOCK_DET_EN_SHIFT;
1238         epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1239         epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1240         epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1241
1242         /*
1243          * Required period ( in cycles) to genarate a stable clock output.
1244          * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1245          * frequency input (as per spec)
1246          */
1247         lockcnt = 3000 * exynos5_epll_div[i].p_div;
1248
1249         writel(lockcnt, &clk->epll_lock);
1250         writel(epll_con, &clk->epll_con0);
1251         writel(epll_con_k, &clk->epll_con1);
1252
1253         start = get_timer(0);
1254
1255          while (!(readl(&clk->epll_con0) &
1256                         (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1257                 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1258                         debug("%s: Timeout waiting for EPLL lock\n", __func__);
1259                         return -1;
1260                 }
1261         }
1262         return 0;
1263 }
1264
1265 int exynos5_set_i2s_clk_source(unsigned int i2s_id)
1266 {
1267         struct exynos5_clock *clk =
1268                 (struct exynos5_clock *)samsung_get_base_clock();
1269         unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
1270
1271         if (i2s_id == 0) {
1272                 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
1273                 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
1274                                 (CLK_SRC_SCLK_EPLL));
1275                 setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
1276         } else if (i2s_id == 1) {
1277                 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1278                                 (CLK_SRC_SCLK_EPLL));
1279         } else {
1280                 return -1;
1281         }
1282         return 0;
1283 }
1284
1285 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1286                                   unsigned int dst_frq,
1287                                   unsigned int i2s_id)
1288 {
1289         struct exynos5_clock *clk =
1290                 (struct exynos5_clock *)samsung_get_base_clock();
1291         unsigned int div;
1292
1293         if ((dst_frq == 0) || (src_frq == 0)) {
1294                 debug("%s: Invalid requency input for prescaler\n", __func__);
1295                 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1296                 return -1;
1297         }
1298
1299         div = (src_frq / dst_frq);
1300         if (i2s_id == 0) {
1301                 if (div > AUDIO_0_RATIO_MASK) {
1302                         debug("%s: Frequency ratio is out of range\n",
1303                               __func__);
1304                         debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1305                         return -1;
1306                 }
1307                 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
1308                                 (div & AUDIO_0_RATIO_MASK));
1309         } else if(i2s_id == 1) {
1310                 if (div > AUDIO_1_RATIO_MASK) {
1311                         debug("%s: Frequency ratio is out of range\n",
1312                               __func__);
1313                         debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1314                         return -1;
1315                 }
1316                 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1317                                 (div & AUDIO_1_RATIO_MASK));
1318         } else {
1319                 return -1;
1320         }
1321         return 0;
1322 }
1323
1324 /**
1325  * Linearly searches for the most accurate main and fine stage clock scalars
1326  * (divisors) for a specified target frequency and scalar bit sizes by checking
1327  * all multiples of main_scalar_bits values. Will always return scalars up to or
1328  * slower than target.
1329  *
1330  * @param main_scalar_bits      Number of main scalar bits, must be > 0 and < 32
1331  * @param fine_scalar_bits      Number of fine scalar bits, must be > 0 and < 32
1332  * @param input_freq            Clock frequency to be scaled in Hz
1333  * @param target_freq           Desired clock frequency in Hz
1334  * @param best_fine_scalar      Pointer to store the fine stage divisor
1335  *
1336  * @return best_main_scalar     Main scalar for desired frequency or -1 if none
1337  * found
1338  */
1339 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1340         unsigned int fine_scalar_bits, unsigned int input_rate,
1341         unsigned int target_rate, unsigned int *best_fine_scalar)
1342 {
1343         int i;
1344         int best_main_scalar = -1;
1345         unsigned int best_error = target_rate;
1346         const unsigned int cap = (1 << fine_scalar_bits) - 1;
1347         const unsigned int loops = 1 << main_scaler_bits;
1348
1349         debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1350                         target_rate, cap);
1351
1352         assert(best_fine_scalar != NULL);
1353         assert(main_scaler_bits <= fine_scalar_bits);
1354
1355         *best_fine_scalar = 1;
1356
1357         if (input_rate == 0 || target_rate == 0)
1358                 return -1;
1359
1360         if (target_rate >= input_rate)
1361                 return 1;
1362
1363         for (i = 1; i <= loops; i++) {
1364                 const unsigned int effective_div =
1365                         max(min(input_rate / i / target_rate, cap), 1U);
1366                 const unsigned int effective_rate = input_rate / i /
1367                                                         effective_div;
1368                 const int error = target_rate - effective_rate;
1369
1370                 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1371                                 effective_rate, error);
1372
1373                 if (error >= 0 && error <= best_error) {
1374                         best_error = error;
1375                         best_main_scalar = i;
1376                         *best_fine_scalar = effective_div;
1377                 }
1378         }
1379
1380         return best_main_scalar;
1381 }
1382
1383 static int exynos5_set_spi_clk(enum periph_id periph_id,
1384                                         unsigned int rate)
1385 {
1386         struct exynos5_clock *clk =
1387                 (struct exynos5_clock *)samsung_get_base_clock();
1388         int main;
1389         unsigned int fine;
1390         unsigned shift, pre_shift;
1391         unsigned mask = 0xff;
1392         u32 *reg;
1393
1394         main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1395         if (main < 0) {
1396                 debug("%s: Cannot set clock rate for periph %d",
1397                                 __func__, periph_id);
1398                 return -1;
1399         }
1400         main = main - 1;
1401         fine = fine - 1;
1402
1403         switch (periph_id) {
1404         case PERIPH_ID_SPI0:
1405                 reg = &clk->div_peric1;
1406                 shift = 0;
1407                 pre_shift = 8;
1408                 break;
1409         case PERIPH_ID_SPI1:
1410                 reg = &clk->div_peric1;
1411                 shift = 16;
1412                 pre_shift = 24;
1413                 break;
1414         case PERIPH_ID_SPI2:
1415                 reg = &clk->div_peric2;
1416                 shift = 0;
1417                 pre_shift = 8;
1418                 break;
1419         case PERIPH_ID_SPI3:
1420                 reg = &clk->sclk_div_isp;
1421                 shift = 0;
1422                 pre_shift = 4;
1423                 break;
1424         case PERIPH_ID_SPI4:
1425                 reg = &clk->sclk_div_isp;
1426                 shift = 12;
1427                 pre_shift = 16;
1428                 break;
1429         default:
1430                 debug("%s: Unsupported peripheral ID %d\n", __func__,
1431                       periph_id);
1432                 return -1;
1433         }
1434         clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1435         clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1436
1437         return 0;
1438 }
1439
1440 static int exynos5420_set_spi_clk(enum periph_id periph_id,
1441                                         unsigned int rate)
1442 {
1443         struct exynos5420_clock *clk =
1444                 (struct exynos5420_clock *)samsung_get_base_clock();
1445         int main;
1446         unsigned int fine;
1447         unsigned shift, pre_shift;
1448         unsigned div_mask = 0xf, pre_div_mask = 0xff;
1449         u32 *reg;
1450         u32 *pre_reg;
1451
1452         main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1453         if (main < 0) {
1454                 debug("%s: Cannot set clock rate for periph %d",
1455                       __func__, periph_id);
1456                 return -1;
1457         }
1458         main = main - 1;
1459         fine = fine - 1;
1460
1461         switch (periph_id) {
1462         case PERIPH_ID_SPI0:
1463                 reg = &clk->div_peric1;
1464                 shift = 20;
1465                 pre_reg = &clk->div_peric4;
1466                 pre_shift = 8;
1467                 break;
1468         case PERIPH_ID_SPI1:
1469                 reg = &clk->div_peric1;
1470                 shift = 24;
1471                 pre_reg = &clk->div_peric4;
1472                 pre_shift = 16;
1473                 break;
1474         case PERIPH_ID_SPI2:
1475                 reg = &clk->div_peric1;
1476                 shift = 28;
1477                 pre_reg = &clk->div_peric4;
1478                 pre_shift = 24;
1479                 break;
1480         case PERIPH_ID_SPI3:
1481                 reg = &clk->div_isp1;
1482                 shift = 16;
1483                 pre_reg = &clk->div_isp1;
1484                 pre_shift = 0;
1485                 break;
1486         case PERIPH_ID_SPI4:
1487                 reg = &clk->div_isp1;
1488                 shift = 20;
1489                 pre_reg = &clk->div_isp1;
1490                 pre_shift = 8;
1491                 break;
1492         default:
1493                 debug("%s: Unsupported peripheral ID %d\n", __func__,
1494                       periph_id);
1495                 return -1;
1496         }
1497
1498         clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
1499         clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
1500                         (fine & pre_div_mask) << pre_shift);
1501
1502         return 0;
1503 }
1504
1505 static unsigned long exynos4_get_i2c_clk(void)
1506 {
1507         struct exynos4_clock *clk =
1508                 (struct exynos4_clock *)samsung_get_base_clock();
1509         unsigned long sclk, aclk_100;
1510         unsigned int ratio;
1511
1512         sclk = get_pll_clk(APLL);
1513
1514         ratio = (readl(&clk->div_top)) >> 4;
1515         ratio &= 0xf;
1516         aclk_100 = sclk / (ratio + 1);
1517         return aclk_100;
1518 }
1519
1520 unsigned long get_pll_clk(int pllreg)
1521 {
1522         if (cpu_is_exynos5()) {
1523                 if (proid_is_exynos5420() || proid_is_exynos5800())
1524                         return exynos542x_get_pll_clk(pllreg);
1525                 return exynos5_get_pll_clk(pllreg);
1526         } else {
1527                 if (proid_is_exynos4412())
1528                         return exynos4x12_get_pll_clk(pllreg);
1529                 return exynos4_get_pll_clk(pllreg);
1530         }
1531 }
1532
1533 unsigned long get_arm_clk(void)
1534 {
1535         if (cpu_is_exynos5())
1536                 return exynos5_get_arm_clk();
1537         else {
1538                 if (proid_is_exynos4412())
1539                         return exynos4x12_get_arm_clk();
1540                 return exynos4_get_arm_clk();
1541         }
1542 }
1543
1544 unsigned long get_i2c_clk(void)
1545 {
1546         if (cpu_is_exynos5()) {
1547                 return clock_get_periph_rate(PERIPH_ID_I2C0);
1548         } else if (cpu_is_exynos4()) {
1549                 return exynos4_get_i2c_clk();
1550         } else {
1551                 debug("I2C clock is not set for this CPU\n");
1552                 return 0;
1553         }
1554 }
1555
1556 unsigned long get_pwm_clk(void)
1557 {
1558         if (cpu_is_exynos5()) {
1559                 return clock_get_periph_rate(PERIPH_ID_PWM0);
1560         } else {
1561                 if (proid_is_exynos4412())
1562                         return exynos4x12_get_pwm_clk();
1563                 return exynos4_get_pwm_clk();
1564         }
1565 }
1566
1567 unsigned long get_uart_clk(int dev_index)
1568 {
1569         enum periph_id id;
1570
1571         switch (dev_index) {
1572         case 0:
1573                 id = PERIPH_ID_UART0;
1574                 break;
1575         case 1:
1576                 id = PERIPH_ID_UART1;
1577                 break;
1578         case 2:
1579                 id = PERIPH_ID_UART2;
1580                 break;
1581         case 3:
1582                 id = PERIPH_ID_UART3;
1583                 break;
1584         default:
1585                 debug("%s: invalid UART index %d", __func__, dev_index);
1586                 return -1;
1587         }
1588
1589         if (cpu_is_exynos5()) {
1590                 return clock_get_periph_rate(id);
1591         } else {
1592                 if (proid_is_exynos4412())
1593                         return exynos4x12_get_uart_clk(dev_index);
1594                 return exynos4_get_uart_clk(dev_index);
1595         }
1596 }
1597
1598 unsigned long get_mmc_clk(int dev_index)
1599 {
1600         enum periph_id id;
1601
1602         switch (dev_index) {
1603         case 0:
1604                 id = PERIPH_ID_SDMMC0;
1605                 break;
1606         case 1:
1607                 id = PERIPH_ID_SDMMC1;
1608                 break;
1609         case 2:
1610                 id = PERIPH_ID_SDMMC2;
1611                 break;
1612         case 3:
1613                 id = PERIPH_ID_SDMMC3;
1614                 break;
1615         default:
1616                 debug("%s: invalid MMC index %d", __func__, dev_index);
1617                 return -1;
1618         }
1619
1620         if (cpu_is_exynos5()) {
1621                 return clock_get_periph_rate(id);
1622         } else {
1623                 return exynos4_get_mmc_clk(dev_index);
1624         }
1625 }
1626
1627 void set_mmc_clk(int dev_index, unsigned int div)
1628 {
1629         /* If want to set correct value, it needs to substract one from div.*/
1630         if (div > 0)
1631                 div -= 1;
1632
1633         if (cpu_is_exynos5()) {
1634                 if (proid_is_exynos5420() || proid_is_exynos5800())
1635                         exynos5420_set_mmc_clk(dev_index, div);
1636                 else
1637                         exynos5_set_mmc_clk(dev_index, div);
1638         } else {
1639                 exynos4_set_mmc_clk(dev_index, div);
1640         }
1641 }
1642
1643 unsigned long get_lcd_clk(void)
1644 {
1645         if (cpu_is_exynos4())
1646                 return exynos4_get_lcd_clk();
1647         else {
1648                 if (proid_is_exynos5420() || proid_is_exynos5800())
1649                         return exynos5420_get_lcd_clk();
1650                 else
1651                         return exynos5_get_lcd_clk();
1652         }
1653 }
1654
1655 void set_lcd_clk(void)
1656 {
1657         if (cpu_is_exynos4())
1658                 exynos4_set_lcd_clk();
1659         else {
1660                 if (proid_is_exynos5250())
1661                         exynos5_set_lcd_clk();
1662                 else if (proid_is_exynos5420() || proid_is_exynos5800())
1663                         exynos5420_set_lcd_clk();
1664         }
1665 }
1666
1667 void set_mipi_clk(void)
1668 {
1669         if (cpu_is_exynos4())
1670                 exynos4_set_mipi_clk();
1671 }
1672
1673 int set_spi_clk(int periph_id, unsigned int rate)
1674 {
1675         if (cpu_is_exynos5()) {
1676                 if (proid_is_exynos5420() || proid_is_exynos5800())
1677                         return exynos5420_set_spi_clk(periph_id, rate);
1678                 return exynos5_set_spi_clk(periph_id, rate);
1679         } else {
1680                 return 0;
1681         }
1682 }
1683
1684 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
1685                           unsigned int i2s_id)
1686 {
1687         if (cpu_is_exynos5())
1688                 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
1689         else
1690                 return 0;
1691 }
1692
1693 int set_i2s_clk_source(unsigned int i2s_id)
1694 {
1695         if (cpu_is_exynos5())
1696                 return exynos5_set_i2s_clk_source(i2s_id);
1697         else
1698                 return 0;
1699 }
1700
1701 int set_epll_clk(unsigned long rate)
1702 {
1703         if (cpu_is_exynos5())
1704                 return exynos5_set_epll_clk(rate);
1705         else
1706                 return 0;
1707 }