2 * Copyright (C) 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/clk.h>
12 #include <asm/arch/periph.h>
14 #define PLL_DIV_1024 1024
15 #define PLL_DIV_65535 65535
16 #define PLL_DIV_65536 65536
19 * This structure is to store the src bit, div bit and prediv bit
20 * positions of the peripheral clocks of the src and div registers
28 /* src_bit div_bit prediv_bit */
29 static struct clk_bit_info clk_bit_info[] = {
61 /* Epll Clock division values to achive different frequency output */
62 static struct set_epll_con_val exynos5_epll_div[] = {
63 { 192000000, 0, 48, 3, 1, 0 },
64 { 180000000, 0, 45, 3, 1, 0 },
65 { 73728000, 1, 73, 3, 3, 47710 },
66 { 67737600, 1, 90, 4, 3, 20762 },
67 { 49152000, 0, 49, 3, 3, 9961 },
68 { 45158400, 0, 45, 3, 3, 10381 },
69 { 180633600, 0, 45, 3, 1, 10381 }
72 /* exynos: return pll clock frequency */
73 static int exynos_get_pll_clk(int pllreg, unsigned int r, unsigned int k)
75 unsigned long m, p, s = 0, mask, fout;
79 * APLL_CON: MIDV [25:16]
80 * MPLL_CON: MIDV [25:16]
81 * EPLL_CON: MIDV [24:16]
82 * VPLL_CON: MIDV [24:16]
83 * BPLL_CON: MIDV [25:16]: Exynos5
85 if (pllreg == APLL || pllreg == MPLL || pllreg == BPLL ||
98 freq = CONFIG_SYS_CLK_FREQ;
100 if (pllreg == EPLL || pllreg == RPLL) {
102 /* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
103 fout = (m + k / PLL_DIV_65536) * (freq / (p * (1 << s)));
104 } else if (pllreg == VPLL) {
109 * FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV)
112 * FOUT = (MDIV + K / 65535) * FIN / (PDIV * 2^SDIV)
115 * FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV)
117 if (proid_is_exynos4210())
119 else if (proid_is_exynos4412())
121 else if (proid_is_exynos5250() || proid_is_exynos5420()
122 || proid_is_exynos5800())
127 fout = (m + k / div) * (freq / (p * (1 << s)));
130 * Exynos4412 / Exynos5250
131 * FOUT = MDIV * FIN / (PDIV * 2^SDIV)
134 * FOUT = MDIV * FIN / (PDIV * 2^(SDIV-1))
136 if (proid_is_exynos4210())
137 fout = m * (freq / (p * (1 << (s - 1))));
139 fout = m * (freq / (p * (1 << s)));
144 /* exynos4: return pll clock frequency */
145 static unsigned long exynos4_get_pll_clk(int pllreg)
147 struct exynos4_clock *clk =
148 (struct exynos4_clock *)samsung_get_base_clock();
149 unsigned long r, k = 0;
153 r = readl(&clk->apll_con0);
156 r = readl(&clk->mpll_con0);
159 r = readl(&clk->epll_con0);
160 k = readl(&clk->epll_con1);
163 r = readl(&clk->vpll_con0);
164 k = readl(&clk->vpll_con1);
167 printf("Unsupported PLL (%d)\n", pllreg);
171 return exynos_get_pll_clk(pllreg, r, k);
174 /* exynos4x12: return pll clock frequency */
175 static unsigned long exynos4x12_get_pll_clk(int pllreg)
177 struct exynos4x12_clock *clk =
178 (struct exynos4x12_clock *)samsung_get_base_clock();
179 unsigned long r, k = 0;
183 r = readl(&clk->apll_con0);
186 r = readl(&clk->mpll_con0);
189 r = readl(&clk->epll_con0);
190 k = readl(&clk->epll_con1);
193 r = readl(&clk->vpll_con0);
194 k = readl(&clk->vpll_con1);
197 printf("Unsupported PLL (%d)\n", pllreg);
201 return exynos_get_pll_clk(pllreg, r, k);
204 /* exynos5: return pll clock frequency */
205 static unsigned long exynos5_get_pll_clk(int pllreg)
207 struct exynos5_clock *clk =
208 (struct exynos5_clock *)samsung_get_base_clock();
209 unsigned long r, k = 0, fout;
210 unsigned int pll_div2_sel, fout_sel;
214 r = readl(&clk->apll_con0);
217 r = readl(&clk->mpll_con0);
220 r = readl(&clk->epll_con0);
221 k = readl(&clk->epll_con1);
224 r = readl(&clk->vpll_con0);
225 k = readl(&clk->vpll_con1);
228 r = readl(&clk->bpll_con0);
231 printf("Unsupported PLL (%d)\n", pllreg);
235 fout = exynos_get_pll_clk(pllreg, r, k);
237 /* According to the user manual, in EVT1 MPLL and BPLL always gives
238 * 1.6GHz clock, so divide by 2 to get 800MHz MPLL clock.*/
239 if (pllreg == MPLL || pllreg == BPLL) {
240 pll_div2_sel = readl(&clk->pll_div2_sel);
244 fout_sel = (pll_div2_sel >> MPLL_FOUT_SEL_SHIFT)
245 & MPLL_FOUT_SEL_MASK;
248 fout_sel = (pll_div2_sel >> BPLL_FOUT_SEL_SHIFT)
249 & BPLL_FOUT_SEL_MASK;
263 static unsigned long exynos5_get_periph_rate(int peripheral)
265 struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
266 unsigned long sclk, sub_clk;
267 unsigned int src, div, sub_div;
268 struct exynos5_clock *clk =
269 (struct exynos5_clock *)samsung_get_base_clock();
271 switch (peripheral) {
272 case PERIPH_ID_UART0:
273 case PERIPH_ID_UART1:
274 case PERIPH_ID_UART2:
275 case PERIPH_ID_UART3:
276 src = readl(&clk->src_peric0);
277 div = readl(&clk->div_peric0);
284 src = readl(&clk->src_peric0);
285 div = readl(&clk->div_peric3);
288 src = readl(&clk->src_mau);
289 div = readl(&clk->div_mau);
292 src = readl(&clk->src_peric1);
293 div = readl(&clk->div_peric1);
296 src = readl(&clk->src_peric1);
297 div = readl(&clk->div_peric2);
301 src = readl(&clk->sclk_src_isp);
302 div = readl(&clk->sclk_div_isp);
304 case PERIPH_ID_SDMMC0:
305 case PERIPH_ID_SDMMC1:
306 case PERIPH_ID_SDMMC2:
307 case PERIPH_ID_SDMMC3:
308 src = readl(&clk->src_fsys);
309 div = readl(&clk->div_fsys1);
319 sclk = exynos5_get_pll_clk(MPLL);
320 sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit)
322 div = ((readl(&clk->div_top0) >> bit_info->prediv_bit)
324 return (sclk / sub_div) / div;
326 debug("%s: invalid peripheral %d", __func__, peripheral);
330 src = (src >> bit_info->src_bit) & 0xf;
333 case EXYNOS_SRC_MPLL:
334 sclk = exynos5_get_pll_clk(MPLL);
336 case EXYNOS_SRC_EPLL:
337 sclk = exynos5_get_pll_clk(EPLL);
339 case EXYNOS_SRC_VPLL:
340 sclk = exynos5_get_pll_clk(VPLL);
346 /* Ratio clock division for this peripheral */
347 sub_div = (div >> bit_info->div_bit) & 0xf;
348 sub_clk = sclk / (sub_div + 1);
350 /* Pre-ratio clock division for SDMMC0 and 2 */
351 if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
352 div = (div >> bit_info->prediv_bit) & 0xff;
353 return sub_clk / (div + 1);
359 unsigned long clock_get_periph_rate(int peripheral)
361 if (cpu_is_exynos5())
362 return exynos5_get_periph_rate(peripheral);
367 /* exynos5420: return pll clock frequency */
368 static unsigned long exynos5420_get_pll_clk(int pllreg)
370 struct exynos5420_clock *clk =
371 (struct exynos5420_clock *)samsung_get_base_clock();
372 unsigned long r, k = 0;
376 r = readl(&clk->apll_con0);
379 r = readl(&clk->mpll_con0);
382 r = readl(&clk->epll_con0);
383 k = readl(&clk->epll_con1);
386 r = readl(&clk->vpll_con0);
387 k = readl(&clk->vpll_con1);
390 r = readl(&clk->bpll_con0);
393 r = readl(&clk->rpll_con0);
394 k = readl(&clk->rpll_con1);
397 r = readl(&clk->spll_con0);
400 printf("Unsupported PLL (%d)\n", pllreg);
404 return exynos_get_pll_clk(pllreg, r, k);
407 /* exynos4: return ARM clock frequency */
408 static unsigned long exynos4_get_arm_clk(void)
410 struct exynos4_clock *clk =
411 (struct exynos4_clock *)samsung_get_base_clock();
413 unsigned long armclk;
414 unsigned int core_ratio;
415 unsigned int core2_ratio;
417 div = readl(&clk->div_cpu0);
419 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
420 core_ratio = (div >> 0) & 0x7;
421 core2_ratio = (div >> 28) & 0x7;
423 armclk = get_pll_clk(APLL) / (core_ratio + 1);
424 armclk /= (core2_ratio + 1);
429 /* exynos4x12: return ARM clock frequency */
430 static unsigned long exynos4x12_get_arm_clk(void)
432 struct exynos4x12_clock *clk =
433 (struct exynos4x12_clock *)samsung_get_base_clock();
435 unsigned long armclk;
436 unsigned int core_ratio;
437 unsigned int core2_ratio;
439 div = readl(&clk->div_cpu0);
441 /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
442 core_ratio = (div >> 0) & 0x7;
443 core2_ratio = (div >> 28) & 0x7;
445 armclk = get_pll_clk(APLL) / (core_ratio + 1);
446 armclk /= (core2_ratio + 1);
451 /* exynos5: return ARM clock frequency */
452 static unsigned long exynos5_get_arm_clk(void)
454 struct exynos5_clock *clk =
455 (struct exynos5_clock *)samsung_get_base_clock();
457 unsigned long armclk;
458 unsigned int arm_ratio;
459 unsigned int arm2_ratio;
461 div = readl(&clk->div_cpu0);
463 /* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
464 arm_ratio = (div >> 0) & 0x7;
465 arm2_ratio = (div >> 28) & 0x7;
467 armclk = get_pll_clk(APLL) / (arm_ratio + 1);
468 armclk /= (arm2_ratio + 1);
473 /* exynos4: return pwm clock frequency */
474 static unsigned long exynos4_get_pwm_clk(void)
476 struct exynos4_clock *clk =
477 (struct exynos4_clock *)samsung_get_base_clock();
478 unsigned long pclk, sclk;
482 if (s5p_get_cpu_rev() == 0) {
487 sel = readl(&clk->src_peril0);
488 sel = (sel >> 24) & 0xf;
491 sclk = get_pll_clk(MPLL);
493 sclk = get_pll_clk(EPLL);
495 sclk = get_pll_clk(VPLL);
503 ratio = readl(&clk->div_peril3);
505 } else if (s5p_get_cpu_rev() == 1) {
506 sclk = get_pll_clk(MPLL);
511 pclk = sclk / (ratio + 1);
516 /* exynos4x12: return pwm clock frequency */
517 static unsigned long exynos4x12_get_pwm_clk(void)
519 unsigned long pclk, sclk;
522 sclk = get_pll_clk(MPLL);
525 pclk = sclk / (ratio + 1);
530 /* exynos5420: return pwm clock frequency */
531 static unsigned long exynos5420_get_pwm_clk(void)
533 struct exynos5420_clock *clk =
534 (struct exynos5420_clock *)samsung_get_base_clock();
535 unsigned long pclk, sclk;
542 ratio = readl(&clk->div_peric0);
543 ratio = (ratio >> 28) & 0xf;
544 sclk = get_pll_clk(MPLL);
546 pclk = sclk / (ratio + 1);
551 /* exynos4: return uart clock frequency */
552 static unsigned long exynos4_get_uart_clk(int dev_index)
554 struct exynos4_clock *clk =
555 (struct exynos4_clock *)samsung_get_base_clock();
556 unsigned long uclk, sclk;
569 sel = readl(&clk->src_peril0);
570 sel = (sel >> (dev_index << 2)) & 0xf;
573 sclk = get_pll_clk(MPLL);
575 sclk = get_pll_clk(EPLL);
577 sclk = get_pll_clk(VPLL);
586 * UART3_RATIO [12:15]
587 * UART4_RATIO [16:19]
588 * UART5_RATIO [23:20]
590 ratio = readl(&clk->div_peril0);
591 ratio = (ratio >> (dev_index << 2)) & 0xf;
593 uclk = sclk / (ratio + 1);
598 /* exynos4x12: return uart clock frequency */
599 static unsigned long exynos4x12_get_uart_clk(int dev_index)
601 struct exynos4x12_clock *clk =
602 (struct exynos4x12_clock *)samsung_get_base_clock();
603 unsigned long uclk, sclk;
615 sel = readl(&clk->src_peril0);
616 sel = (sel >> (dev_index << 2)) & 0xf;
619 sclk = get_pll_clk(MPLL);
621 sclk = get_pll_clk(EPLL);
623 sclk = get_pll_clk(VPLL);
632 * UART3_RATIO [12:15]
633 * UART4_RATIO [16:19]
635 ratio = readl(&clk->div_peril0);
636 ratio = (ratio >> (dev_index << 2)) & 0xf;
638 uclk = sclk / (ratio + 1);
643 /* exynos5: return uart clock frequency */
644 static unsigned long exynos5_get_uart_clk(int dev_index)
646 struct exynos5_clock *clk =
647 (struct exynos5_clock *)samsung_get_base_clock();
648 unsigned long uclk, sclk;
661 sel = readl(&clk->src_peric0);
662 sel = (sel >> (dev_index << 2)) & 0xf;
665 sclk = get_pll_clk(MPLL);
667 sclk = get_pll_clk(EPLL);
669 sclk = get_pll_clk(VPLL);
678 * UART3_RATIO [12:15]
679 * UART4_RATIO [16:19]
680 * UART5_RATIO [23:20]
682 ratio = readl(&clk->div_peric0);
683 ratio = (ratio >> (dev_index << 2)) & 0xf;
685 uclk = sclk / (ratio + 1);
690 /* exynos5420: return uart clock frequency */
691 static unsigned long exynos5420_get_uart_clk(int dev_index)
693 struct exynos5420_clock *clk =
694 (struct exynos5420_clock *)samsung_get_base_clock();
695 unsigned long uclk, sclk;
705 * generalised calculation as follows
706 * sel = (sel >> ((dev_index * 4) + 4)) & mask;
708 sel = readl(&clk->src_peric0);
709 sel = (sel >> ((dev_index * 4) + 4)) & 0x7;
712 sclk = get_pll_clk(MPLL);
714 sclk = get_pll_clk(EPLL);
716 sclk = get_pll_clk(RPLL);
723 * UART1_RATIO [15:12]
724 * UART2_RATIO [19:16]
725 * UART3_RATIO [23:20]
726 * generalised calculation as follows
727 * ratio = (ratio >> ((dev_index * 4) + 8)) & mask;
729 ratio = readl(&clk->div_peric0);
730 ratio = (ratio >> ((dev_index * 4) + 8)) & 0xf;
732 uclk = sclk / (ratio + 1);
737 static unsigned long exynos4_get_mmc_clk(int dev_index)
739 struct exynos4_clock *clk =
740 (struct exynos4_clock *)samsung_get_base_clock();
741 unsigned long uclk, sclk;
742 unsigned int sel, ratio, pre_ratio;
745 sel = readl(&clk->src_fsys);
746 sel = (sel >> (dev_index << 2)) & 0xf;
749 sclk = get_pll_clk(MPLL);
751 sclk = get_pll_clk(EPLL);
753 sclk = get_pll_clk(VPLL);
760 ratio = readl(&clk->div_fsys1);
761 pre_ratio = readl(&clk->div_fsys1);
765 ratio = readl(&clk->div_fsys2);
766 pre_ratio = readl(&clk->div_fsys2);
769 ratio = readl(&clk->div_fsys3);
770 pre_ratio = readl(&clk->div_fsys3);
776 if (dev_index == 1 || dev_index == 3)
779 ratio = (ratio >> shift) & 0xf;
780 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
781 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
786 static unsigned long exynos5_get_mmc_clk(int dev_index)
788 struct exynos5_clock *clk =
789 (struct exynos5_clock *)samsung_get_base_clock();
790 unsigned long uclk, sclk;
791 unsigned int sel, ratio, pre_ratio;
794 sel = readl(&clk->src_fsys);
795 sel = (sel >> (dev_index << 2)) & 0xf;
798 sclk = get_pll_clk(MPLL);
800 sclk = get_pll_clk(EPLL);
802 sclk = get_pll_clk(VPLL);
809 ratio = readl(&clk->div_fsys1);
810 pre_ratio = readl(&clk->div_fsys1);
814 ratio = readl(&clk->div_fsys2);
815 pre_ratio = readl(&clk->div_fsys2);
821 if (dev_index == 1 || dev_index == 3)
824 ratio = (ratio >> shift) & 0xf;
825 pre_ratio = (pre_ratio >> (shift + 8)) & 0xff;
826 uclk = (sclk / (ratio + 1)) / (pre_ratio + 1);
831 static unsigned long exynos5420_get_mmc_clk(int dev_index)
833 struct exynos5420_clock *clk =
834 (struct exynos5420_clock *)samsung_get_base_clock();
835 unsigned long uclk, sclk;
836 unsigned int sel, ratio;
843 * generalised calculation as follows
844 * sel = (sel >> ((dev_index * 4) + 8)) & mask
846 sel = readl(&clk->src_fsys);
847 sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
850 sclk = get_pll_clk(MPLL);
852 sclk = get_pll_clk(EPLL);
861 * generalised calculation as follows
862 * ratio = (ratio >> (dev_index * 10)) & mask
864 ratio = readl(&clk->div_fsys1);
865 ratio = (ratio >> (dev_index * 10)) & 0x3ff;
867 uclk = (sclk / (ratio + 1));
872 /* exynos4: set the mmc clock */
873 static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
875 struct exynos4_clock *clk =
876 (struct exynos4_clock *)samsung_get_base_clock();
877 unsigned int addr, clear_bit, set_bit;
881 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
883 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
888 addr = (unsigned int)&clk->div_fsys1;
889 clear_bit = MASK_PRE_RATIO(dev_index);
890 set_bit = SET_PRE_RATIO(dev_index, div);
891 } else if (dev_index == 4) {
892 addr = (unsigned int)&clk->div_fsys3;
894 /* MMC4 is controlled with the MMC4_RATIO value */
895 clear_bit = MASK_RATIO(dev_index);
896 set_bit = SET_RATIO(dev_index, div);
898 addr = (unsigned int)&clk->div_fsys2;
900 clear_bit = MASK_PRE_RATIO(dev_index);
901 set_bit = SET_PRE_RATIO(dev_index, div);
904 clrsetbits_le32(addr, clear_bit, set_bit);
907 /* exynos5: set the mmc clock */
908 static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
910 struct exynos5_clock *clk =
911 (struct exynos5_clock *)samsung_get_base_clock();
916 * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
918 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
921 addr = (unsigned int)&clk->div_fsys1;
923 addr = (unsigned int)&clk->div_fsys2;
927 clrsetbits_le32(addr, 0xff << ((dev_index << 4) + 8),
928 (div & 0xff) << ((dev_index << 4) + 8));
931 /* exynos5: set the mmc clock */
932 static void exynos5420_set_mmc_clk(int dev_index, unsigned int div)
934 struct exynos5420_clock *clk =
935 (struct exynos5420_clock *)samsung_get_base_clock();
945 addr = (unsigned int)&clk->div_fsys1;
946 shift = dev_index * 10;
948 clrsetbits_le32(addr, 0x3ff << shift, (div & 0x3ff) << shift);
951 /* get_lcd_clk: return lcd clock frequency */
952 static unsigned long exynos4_get_lcd_clk(void)
954 struct exynos4_clock *clk =
955 (struct exynos4_clock *)samsung_get_base_clock();
956 unsigned long pclk, sclk;
964 sel = readl(&clk->src_lcd0);
973 sclk = get_pll_clk(MPLL);
975 sclk = get_pll_clk(EPLL);
977 sclk = get_pll_clk(VPLL);
985 ratio = readl(&clk->div_lcd0);
988 pclk = sclk / (ratio + 1);
993 /* get_lcd_clk: return lcd clock frequency */
994 static unsigned long exynos5_get_lcd_clk(void)
996 struct exynos5_clock *clk =
997 (struct exynos5_clock *)samsung_get_base_clock();
998 unsigned long pclk, sclk;
1006 sel = readl(&clk->src_disp1_0);
1015 sclk = get_pll_clk(MPLL);
1016 else if (sel == 0x7)
1017 sclk = get_pll_clk(EPLL);
1018 else if (sel == 0x8)
1019 sclk = get_pll_clk(VPLL);
1027 ratio = readl(&clk->div_disp1_0);
1028 ratio = ratio & 0xf;
1030 pclk = sclk / (ratio + 1);
1035 static unsigned long exynos5420_get_lcd_clk(void)
1037 struct exynos5420_clock *clk =
1038 (struct exynos5420_clock *)samsung_get_base_clock();
1039 unsigned long pclk, sclk;
1049 sel = readl(&clk->src_disp10);
1053 sclk = get_pll_clk(SPLL);
1055 sclk = get_pll_clk(RPLL);
1061 ratio = readl(&clk->div_disp10);
1062 ratio = ratio & 0xf;
1064 pclk = sclk / (ratio + 1);
1069 void exynos4_set_lcd_clk(void)
1071 struct exynos4_clock *clk =
1072 (struct exynos4_clock *)samsung_get_base_clock();
1084 setbits_le32(&clk->gate_block, 1 << 4);
1090 * MDNIE_PWM0_SEL [8:11]
1092 * set lcd0 src clock 0x6: SCLK_MPLL
1094 clrsetbits_le32(&clk->src_lcd0, 0xf, 0x6);
1104 * Gating all clocks for FIMD0
1106 setbits_le32(&clk->gate_ip_lcd0, 1 << 0);
1111 * MDNIE0_RATIO [7:4]
1112 * MDNIE_PWM0_RATIO [11:8]
1113 * MDNIE_PWM_PRE_RATIO [15:12]
1114 * MIPI0_RATIO [19:16]
1115 * MIPI0_PRE_RATIO [23:20]
1118 clrsetbits_le32(&clk->div_lcd0, 0xf, 0x1);
1121 void exynos5_set_lcd_clk(void)
1123 struct exynos5_clock *clk =
1124 (struct exynos5_clock *)samsung_get_base_clock();
1136 setbits_le32(&clk->gate_block, 1 << 4);
1142 * MDNIE_PWM0_SEL [8:11]
1144 * set lcd0 src clock 0x6: SCLK_MPLL
1146 clrsetbits_le32(&clk->src_disp1_0, 0xf, 0x6);
1156 * Gating all clocks for FIMD0
1158 setbits_le32(&clk->gate_ip_disp1, 1 << 0);
1163 * MDNIE0_RATIO [7:4]
1164 * MDNIE_PWM0_RATIO [11:8]
1165 * MDNIE_PWM_PRE_RATIO [15:12]
1166 * MIPI0_RATIO [19:16]
1167 * MIPI0_PRE_RATIO [23:20]
1170 clrsetbits_le32(&clk->div_disp1_0, 0xf, 0x0);
1173 void exynos5420_set_lcd_clk(void)
1175 struct exynos5420_clock *clk =
1176 (struct exynos5420_clock *)samsung_get_base_clock();
1185 cfg = readl(&clk->src_disp10);
1188 writel(cfg, &clk->src_disp10);
1194 cfg = readl(&clk->div_disp10);
1197 writel(cfg, &clk->div_disp10);
1200 void exynos4_set_mipi_clk(void)
1202 struct exynos4_clock *clk =
1203 (struct exynos4_clock *)samsung_get_base_clock();
1209 * MDNIE_PWM0_SEL [8:11]
1211 * set mipi0 src clock 0x6: SCLK_MPLL
1213 clrsetbits_le32(&clk->src_lcd0, 0xf << 12, 0x6 << 12);
1219 * MDNIE_PWM0_MASK [8]
1221 * set src mask mipi0 0x1: Unmask
1223 setbits_le32(&clk->src_mask_lcd0, 0x1 << 12);
1233 * Gating all clocks for MIPI0
1235 setbits_le32(&clk->gate_ip_lcd0, 1 << 3);
1240 * MDNIE0_RATIO [7:4]
1241 * MDNIE_PWM0_RATIO [11:8]
1242 * MDNIE_PWM_PRE_RATIO [15:12]
1243 * MIPI0_RATIO [19:16]
1244 * MIPI0_PRE_RATIO [23:20]
1247 clrsetbits_le32(&clk->div_lcd0, 0xf << 16, 0x1 << 16);
1253 * exynos5: obtaining the I2C clock
1255 static unsigned long exynos5_get_i2c_clk(void)
1257 struct exynos5_clock *clk =
1258 (struct exynos5_clock *)samsung_get_base_clock();
1259 unsigned long aclk_66, aclk_66_pre, sclk;
1262 sclk = get_pll_clk(MPLL);
1264 ratio = (readl(&clk->div_top1)) >> 24;
1266 aclk_66_pre = sclk / (ratio + 1);
1267 ratio = readl(&clk->div_top0);
1269 aclk_66 = aclk_66_pre / (ratio + 1);
1273 int exynos5_set_epll_clk(unsigned long rate)
1275 unsigned int epll_con, epll_con_k;
1277 unsigned int lockcnt;
1279 struct exynos5_clock *clk =
1280 (struct exynos5_clock *)samsung_get_base_clock();
1282 epll_con = readl(&clk->epll_con0);
1283 epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
1284 EPLL_CON0_LOCK_DET_EN_SHIFT) |
1285 EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
1286 EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT |
1287 EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT);
1289 for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) {
1290 if (exynos5_epll_div[i].freq_out == rate)
1294 if (i == ARRAY_SIZE(exynos5_epll_div))
1297 epll_con_k = exynos5_epll_div[i].k_dsm << 0;
1298 epll_con |= exynos5_epll_div[i].en_lock_det <<
1299 EPLL_CON0_LOCK_DET_EN_SHIFT;
1300 epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT;
1301 epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT;
1302 epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT;
1305 * Required period ( in cycles) to genarate a stable clock output.
1306 * The maximum clock time can be up to 3000 * PDIV cycles of PLLs
1307 * frequency input (as per spec)
1309 lockcnt = 3000 * exynos5_epll_div[i].p_div;
1311 writel(lockcnt, &clk->epll_lock);
1312 writel(epll_con, &clk->epll_con0);
1313 writel(epll_con_k, &clk->epll_con1);
1315 start = get_timer(0);
1317 while (!(readl(&clk->epll_con0) &
1318 (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
1319 if (get_timer(start) > TIMEOUT_EPLL_LOCK) {
1320 debug("%s: Timeout waiting for EPLL lock\n", __func__);
1327 int exynos5_set_i2s_clk_source(unsigned int i2s_id)
1329 struct exynos5_clock *clk =
1330 (struct exynos5_clock *)samsung_get_base_clock();
1331 unsigned int *audio_ass = (unsigned int *)samsung_get_base_audio_ass();
1334 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL);
1335 clrsetbits_le32(&clk->src_mau, AUDIO0_SEL_MASK,
1336 (CLK_SRC_SCLK_EPLL));
1337 setbits_le32(audio_ass, AUDIO_CLKMUX_ASS);
1338 } else if (i2s_id == 1) {
1339 clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
1340 (CLK_SRC_SCLK_EPLL));
1347 int exynos5_set_i2s_clk_prescaler(unsigned int src_frq,
1348 unsigned int dst_frq,
1349 unsigned int i2s_id)
1351 struct exynos5_clock *clk =
1352 (struct exynos5_clock *)samsung_get_base_clock();
1355 if ((dst_frq == 0) || (src_frq == 0)) {
1356 debug("%s: Invalid requency input for prescaler\n", __func__);
1357 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1361 div = (src_frq / dst_frq);
1363 if (div > AUDIO_0_RATIO_MASK) {
1364 debug("%s: Frequency ratio is out of range\n",
1366 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1369 clrsetbits_le32(&clk->div_mau, AUDIO_0_RATIO_MASK,
1370 (div & AUDIO_0_RATIO_MASK));
1371 } else if(i2s_id == 1) {
1372 if (div > AUDIO_1_RATIO_MASK) {
1373 debug("%s: Frequency ratio is out of range\n",
1375 debug("src frq = %d des frq = %d ", src_frq, dst_frq);
1378 clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
1379 (div & AUDIO_1_RATIO_MASK));
1387 * Linearly searches for the most accurate main and fine stage clock scalars
1388 * (divisors) for a specified target frequency and scalar bit sizes by checking
1389 * all multiples of main_scalar_bits values. Will always return scalars up to or
1390 * slower than target.
1392 * @param main_scalar_bits Number of main scalar bits, must be > 0 and < 32
1393 * @param fine_scalar_bits Number of fine scalar bits, must be > 0 and < 32
1394 * @param input_freq Clock frequency to be scaled in Hz
1395 * @param target_freq Desired clock frequency in Hz
1396 * @param best_fine_scalar Pointer to store the fine stage divisor
1398 * @return best_main_scalar Main scalar for desired frequency or -1 if none
1401 static int clock_calc_best_scalar(unsigned int main_scaler_bits,
1402 unsigned int fine_scalar_bits, unsigned int input_rate,
1403 unsigned int target_rate, unsigned int *best_fine_scalar)
1406 int best_main_scalar = -1;
1407 unsigned int best_error = target_rate;
1408 const unsigned int cap = (1 << fine_scalar_bits) - 1;
1409 const unsigned int loops = 1 << main_scaler_bits;
1411 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate,
1414 assert(best_fine_scalar != NULL);
1415 assert(main_scaler_bits <= fine_scalar_bits);
1417 *best_fine_scalar = 1;
1419 if (input_rate == 0 || target_rate == 0)
1422 if (target_rate >= input_rate)
1425 for (i = 1; i <= loops; i++) {
1426 const unsigned int effective_div =
1427 max(min(input_rate / i / target_rate, cap), 1U);
1428 const unsigned int effective_rate = input_rate / i /
1430 const int error = target_rate - effective_rate;
1432 debug("%d|effdiv:%u, effrate:%u, error:%d\n", i, effective_div,
1433 effective_rate, error);
1435 if (error >= 0 && error <= best_error) {
1437 best_main_scalar = i;
1438 *best_fine_scalar = effective_div;
1442 return best_main_scalar;
1445 static int exynos5_set_spi_clk(enum periph_id periph_id,
1448 struct exynos5_clock *clk =
1449 (struct exynos5_clock *)samsung_get_base_clock();
1452 unsigned shift, pre_shift;
1453 unsigned mask = 0xff;
1456 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1458 debug("%s: Cannot set clock rate for periph %d",
1459 __func__, periph_id);
1465 switch (periph_id) {
1466 case PERIPH_ID_SPI0:
1467 reg = &clk->div_peric1;
1471 case PERIPH_ID_SPI1:
1472 reg = &clk->div_peric1;
1476 case PERIPH_ID_SPI2:
1477 reg = &clk->div_peric2;
1481 case PERIPH_ID_SPI3:
1482 reg = &clk->sclk_div_isp;
1486 case PERIPH_ID_SPI4:
1487 reg = &clk->sclk_div_isp;
1492 debug("%s: Unsupported peripheral ID %d\n", __func__,
1496 clrsetbits_le32(reg, mask << shift, (main & mask) << shift);
1497 clrsetbits_le32(reg, mask << pre_shift, (fine & mask) << pre_shift);
1502 static int exynos5420_set_spi_clk(enum periph_id periph_id,
1505 struct exynos5420_clock *clk =
1506 (struct exynos5420_clock *)samsung_get_base_clock();
1509 unsigned shift, pre_shift;
1510 unsigned div_mask = 0xf, pre_div_mask = 0xff;
1514 main = clock_calc_best_scalar(4, 8, 400000000, rate, &fine);
1516 debug("%s: Cannot set clock rate for periph %d",
1517 __func__, periph_id);
1523 switch (periph_id) {
1524 case PERIPH_ID_SPI0:
1525 reg = &clk->div_peric1;
1527 pre_reg = &clk->div_peric4;
1530 case PERIPH_ID_SPI1:
1531 reg = &clk->div_peric1;
1533 pre_reg = &clk->div_peric4;
1536 case PERIPH_ID_SPI2:
1537 reg = &clk->div_peric1;
1539 pre_reg = &clk->div_peric4;
1542 case PERIPH_ID_SPI3:
1543 reg = &clk->div_isp1;
1545 pre_reg = &clk->div_isp1;
1548 case PERIPH_ID_SPI4:
1549 reg = &clk->div_isp1;
1551 pre_reg = &clk->div_isp1;
1555 debug("%s: Unsupported peripheral ID %d\n", __func__,
1560 clrsetbits_le32(reg, div_mask << shift, (main & div_mask) << shift);
1561 clrsetbits_le32(pre_reg, pre_div_mask << pre_shift,
1562 (fine & pre_div_mask) << pre_shift);
1567 static unsigned long exynos4_get_i2c_clk(void)
1569 struct exynos4_clock *clk =
1570 (struct exynos4_clock *)samsung_get_base_clock();
1571 unsigned long sclk, aclk_100;
1574 sclk = get_pll_clk(APLL);
1576 ratio = (readl(&clk->div_top)) >> 4;
1578 aclk_100 = sclk / (ratio + 1);
1582 unsigned long get_pll_clk(int pllreg)
1584 if (cpu_is_exynos5()) {
1585 if (proid_is_exynos5420() || proid_is_exynos5800())
1586 return exynos5420_get_pll_clk(pllreg);
1587 return exynos5_get_pll_clk(pllreg);
1589 if (proid_is_exynos4412())
1590 return exynos4x12_get_pll_clk(pllreg);
1591 return exynos4_get_pll_clk(pllreg);
1595 unsigned long get_arm_clk(void)
1597 if (cpu_is_exynos5())
1598 return exynos5_get_arm_clk();
1600 if (proid_is_exynos4412())
1601 return exynos4x12_get_arm_clk();
1602 return exynos4_get_arm_clk();
1606 unsigned long get_i2c_clk(void)
1608 if (cpu_is_exynos5()) {
1609 return exynos5_get_i2c_clk();
1610 } else if (cpu_is_exynos4()) {
1611 return exynos4_get_i2c_clk();
1613 debug("I2C clock is not set for this CPU\n");
1618 unsigned long get_pwm_clk(void)
1620 if (cpu_is_exynos5()) {
1621 if (proid_is_exynos5420() || proid_is_exynos5800())
1622 return exynos5420_get_pwm_clk();
1623 return clock_get_periph_rate(PERIPH_ID_PWM0);
1625 if (proid_is_exynos4412())
1626 return exynos4x12_get_pwm_clk();
1627 return exynos4_get_pwm_clk();
1631 unsigned long get_uart_clk(int dev_index)
1633 if (cpu_is_exynos5()) {
1634 if (proid_is_exynos5420() || proid_is_exynos5800())
1635 return exynos5420_get_uart_clk(dev_index);
1636 return exynos5_get_uart_clk(dev_index);
1638 if (proid_is_exynos4412())
1639 return exynos4x12_get_uart_clk(dev_index);
1640 return exynos4_get_uart_clk(dev_index);
1644 unsigned long get_mmc_clk(int dev_index)
1646 if (cpu_is_exynos5()) {
1647 if (proid_is_exynos5420() || proid_is_exynos5800())
1648 return exynos5420_get_mmc_clk(dev_index);
1649 return exynos5_get_mmc_clk(dev_index);
1651 return exynos4_get_mmc_clk(dev_index);
1655 void set_mmc_clk(int dev_index, unsigned int div)
1657 if (cpu_is_exynos5()) {
1658 if (proid_is_exynos5420() || proid_is_exynos5800())
1659 exynos5420_set_mmc_clk(dev_index, div);
1661 exynos5_set_mmc_clk(dev_index, div);
1663 exynos4_set_mmc_clk(dev_index, div);
1667 unsigned long get_lcd_clk(void)
1669 if (cpu_is_exynos4())
1670 return exynos4_get_lcd_clk();
1672 if (proid_is_exynos5420() || proid_is_exynos5800())
1673 return exynos5420_get_lcd_clk();
1675 return exynos5_get_lcd_clk();
1679 void set_lcd_clk(void)
1681 if (cpu_is_exynos4())
1682 exynos4_set_lcd_clk();
1684 if (proid_is_exynos5250())
1685 exynos5_set_lcd_clk();
1686 else if (proid_is_exynos5420() || proid_is_exynos5800())
1687 exynos5420_set_lcd_clk();
1691 void set_mipi_clk(void)
1693 if (cpu_is_exynos4())
1694 exynos4_set_mipi_clk();
1697 int set_spi_clk(int periph_id, unsigned int rate)
1699 if (cpu_is_exynos5()) {
1700 if (proid_is_exynos5420() || proid_is_exynos5800())
1701 return exynos5420_set_spi_clk(periph_id, rate);
1702 return exynos5_set_spi_clk(periph_id, rate);
1708 int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
1709 unsigned int i2s_id)
1711 if (cpu_is_exynos5())
1712 return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq, i2s_id);
1717 int set_i2s_clk_source(unsigned int i2s_id)
1719 if (cpu_is_exynos5())
1720 return exynos5_set_i2s_clk_source(i2s_id);
1725 int set_epll_clk(unsigned long rate)
1727 if (cpu_is_exynos5())
1728 return exynos5_set_epll_clk(rate);